• Journal of rehabilitation welfare engineering & assistive technology
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• v.7 no.2
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• pp.13-18
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• 2013

In this paper design a 8 bit Current Steering D/A Converter for stimulating neuron signal. Proposed circuit in paper shows the conversion rate of 10KS/s and the power supply of 3.3V with 0.35um Magna chip CMOS process using full custom layout design. It employes segmented structure which consists of 3bit thermometer decoders and 5bit binary decoder for decreasing glitch noise and increasing resolution. So glitch energy is down by $10nV{\bullet}sec$ rather than binary weighted type DAC. And it makes use of low power current stimulator because of low LSB current. And it can make biphasic signal by connecting with Micro Controller Unit which controls period and amplitude of signal. As result of measurement INL is +0.56/-0.38 LSB and DNL is +0.3/-0.4 LSB. It shows great linearity. Power dissipation is 6mW.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.30 no.8
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• pp.133-140
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• 2002

In this paper, the structure of integrated navigation computer for experiment is proposed. It is designed for considering the real time processing and data storage capacity. It will be used in missile, aircraft, submarine system and experimental vehicle. The I/O device supports IMU, GPS, odometer, altimeter, depth sensor, inclinometer etc. And the main storage device uses the tape device. That can improve the system stability. Therefore it can be used in a high dynamic or shock environment. The embedded linux is used as an Operating System. For the real time capability, sensor data processing and algorithm processing units are seperated. The time synchronization is referenced by IMU data.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.37-42
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• 2000

In this paper, The high-speed, low-Power analog-to-digital conversion structure is proposed using the pipelined comparator away for high-speed conversion rate and the successive- approximation structure for low-power consumption. This structure is the successive-approximation structure using pipelined comparator array to change the reference voltage during the holding time. An 8-bit 10MS/s analog-to-digital converter is designed using 0.8${\mu}{\textrm}{m}$ CMOS technology. The INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41㏈ at a sampling rate of 10MHz with 100KHz sine input signal. The Power consumption is 4.14㎽ at 10MS/s.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.129-138
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• 2014

Various interpolations for digital imaging devices with a single image sensor have proposed. However, conventional methods did not consider the resolution modus of image sensor using periodic sampling. Therefore, the resulting images have problems such as quality degradation and color artifacts(color moire, zipper). In this paper, we propose a color interpolation algorithm for pixel resolution modus of image sensor. The proposed algorithm consisted of an initial step to compensate edge prediction effectively and refinement step using minimum directions for pixel resolution modus. To analyze a result of the proposed algorithm with conventional methods, we evaluated subjectively using images quality comparison and objectively using PSNR(Peak Signal to Noise Ratio). Experimental results showed that the proposed algorithm was more successful in eliminating the color artifacts than conventional methods judged by both objective and subjective criteria.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.3-9
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• 2013

This paper proposes a selective-weighted energy detection (S-WED) and a synchronization algorithm appropriate for it in IR-UWB system. Energy detectors that are practical in terms of implementation are employed widely for noncoherent reception in IR-UWB systems. However, they show low performance due to using the energy samples captured at symbol rate. For this reason, weighted energy detectors are developed to improve the performance of EDs. Hence, for WED, not only synchronization but also the weight coefficients are needed to be obtained prior to data detection. Meanwhile, the optimal weighting coefficients of WEDs are known to be energy values. Therefore, synchronization and the weighting coefficients can be obtained simultaneously. This paper proposes an S-WED and a simple synchronization algorithm for it in which sub-intervals having energies under a certain level are excluded in energy accumulation resulting in a simpler WED with a bit performance increase in low SNR region. The proposed algorithm is verified through simulations using the preamble symbol and channel models defined in the IEEE 802.15.4a.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.5
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• pp.410-418
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• 2017

Results of an analysis of the continuous motion effect for FMCW-SAR system and a signal processing to correct it are presented in this paper. SAR images reconstructed by back-projection algorithm are included as well. To analyze how platform velocity and sampling frequency affect the continuous motion effect, FMCW signal model was used, and the signal processing in time-doppler(t, $k_u$) domain was adopted. Then, back-projection algorithm and modified matched-filter was used to reconstruct SAR images, and it was validated using measured data by airborne FMCW-SAR system in X-band frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.9
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• pp.930-937
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• 2014

Inverse synthetic aperture radar (ISAR) images can be generated by radar which radiates the electromagnetic wave to a target and receives signal reflected from the target. ISAR images can be widely used to target detection and recognition. This paper proposed a method of generation of high resolution ISAR images by synthesizing frequency spectrums of each stepped chirp waveform in one burst and sub-sampling in frequency domain. This process is performed over entire bursts during coherent processing interval. Conventional ISAR image generation method using stepped frequency waveform has a severe problem of short unambiguous range, loading to ghost phenomenon. However, this problem can be resolved by the proposed method. In simulations, we generate high resolution ISAR image of the moving target which is Boeing-737 aircraft model composed of several ideal point scatterers.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.8 no.2
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• pp.91-99
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• 2009

Mobile WiMAX is an emerging technology that can provide ubiquitous Internet access. To provide seamless service in mobile WiMAX environment, delay or disruption in dealing with mobility must be minimized. However offering seamless services on IEEE 802.16e networks is very hard due to long handover latency both in layer 2 and 3. In this paper, we propose a fast cross-layer handover scheme based on prediction algorithm. With the help of the prediction, layer-3 handover activities are able to occur prior to layer-2 handover, and therefore, total handover latency can be reduced. The experiments conducted with system parameters and propagation model defined by WiMAX Forum demonstrate that the proposed method predicts the future signal level accurately and reduces the total handover latency.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.5
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• pp.18-29
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• 2007

The main objective of this paper is to propose a new stability analysis method for a networked control system with multiple packet transmission. The new scheduling method that can guarantee the maximum time delay and discrete switch state equation model which represent a network data loss is proposed. The equivalent model of a MIMO(multi-input multi-output) networked control system is derived from a state space model of linear time invariant interconnected systems in the form of asynchronous dynamical system. Using this model, this paper presents new stability theorems that can determine stability of the networked control system with regard to time delay, data loss, and the number of transmission packets. Simulation results verify the effectiveness of proposed stability analysis method.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.