• The Journal of the Acoustical Society of Korea
• /
• v.23 no.8
• /
• pp.554-561
• /
• 2004

As the technologies of semiconductor and multimedia communication have been improved. the high-quality video and the multi-channel audio have been highlighted. MPEG Audio Layer 3 decoder has been implemented as a Processor using a standard. Since the synthesis filter of MPEG-1 Audio Layer 3 decoder requires the most outstanding operation in the entire decoder. the synthesis filter that can reduce the amount of operation is needed for the design of the high-speed processor. Therefore, in this paper, the synthesis filter. the most important part of MPEG Audio, is materialized in FPGA using the method of DAULT (distributed arithemetic look-up table). For the design of high-speed synthesis filter, the DAULT method is used instead of a multiplier and a Pipeline structure is used. The Performance improvement by 30% is obtained by additionally making the result of multiplication of data with cosine function into the table. All hardware design of this Paper are described using VHDL (VHIC Hardware Description Language) Active-HDL 6.1 of ALDEC is used for VHDL simulation and Synplify Pro 7.2V is used for Model-sim and synthesis. The corresponding library is materialized by XC4013E and XC4020EX. XC4052XL of XILINX and XACT M1.4 is used for P&R tool. The materialized processor operates from 20MHz to 70MHz.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.12B
• /
• pp.1574-1585
• /
• 2011

This paper proposes a real-time algorithm for speed limit sign recognition for advanced safety vehicle system. The proposed algorithm uses Block-DCT in extracting features from a given ROI(Region Of Interest) instead of using entire pixel values as in previous works. The proposed algorithm chooses parts of the DCT coefficients according to the proposed discriminant factor, uses correlation coefficients and variances among ROIs from training samples to reduce amount of arithmetic operations without performance degradation in classification process. The algorithm recognizes the speed limit signs using the information obtained during training process by calculating LDA and Mahalanobis Distance. To increase the hit rate of recognition, it uses accumulated classification results computed for a sequence of frames. Experimental results show that the hit rate of recognition for sequential frames reaches up to 100 %. When compared with previous works, numbers of multiply and add operations are reduced by 69.3 % and 67.9 %, respectively. Start after striking space key 2 times.

• Journal of IKEEE
• /
• v.8 no.2 s.15
• /
• pp.181-185
• /
• 2004

This paper reduces power dissipation with the minimum switching activity of functional units that have many operators. Therefore, it has more effects of power dissipation that operator dissipation to reduce power dissipation of whole circuit preferentially. This paper proposes an algorithm that minimize power dissipation in functional units operations that affect much as power dissipation in VLSI circuit. The algorithm has scheduled operands using power library that has information of all operands. The power library upgrades information of input data in each control step about all inputs of functional units and the information is used at scheduling process. Therefore, the power dissipation is minimized by functional units inputs in optimized data. This paper has applied algorithm that proposed for minimizing power dissipation to functional unit in high level synthesis. The result of experiment has effect of maximum 9.4 % for minimizing power dissipation.

• Journal of Educational Research in Mathematics
• /
• v.17 no.4
• /
• pp.453-475
• /
• 2007

School algebra starts with introducing algebraic expressions which have been one of the cognitive obstacles to the students in the transfer from arithmetic to algebra. In the recent studies on the teaching school algebra, algebraic thinking is getting much more attention together with algebraic expressions. In this paper, we examined the processes of the transfer from arithmetic to algebra and ways for teaching early algebra through algebraic thinking factors. Issues about algebraic thinking have continued since 1980's. But the theoretic foundations for algebraic thinking have not been founded in the previous studies. In this paper, we analyzed the algebraic thinking in school algebra from historico-genetic, epistemological, and symbolic-linguistic points of view, and identified algebraic thinking factors, i.e. the principle of permanence of formal laws, the concept of variable, quantitative reasoning, algebraic interpretation - constructing algebraic expressions, trans formational reasoning - changing algebraic expressions, operational senses - operating algebraic expressions, substitution, etc. We also identified these algebraic thinking factors through analyzing mathematics textbooks of elementary and middle school, and showed the middle school students' low achievement relating to these factors through the algebraic thinking ability test. Based upon these analyses, we argued that the readiness for algebra learning should be made through the processes including algebraic thinking factors in the elementary school and that the transfer from arithmetic to algebra should be accomplished naturally through the pre-algebra course. And we searched for alternative ways to improve algebra curriculums, emphasizing algebraic thinking factors. In summary, we identified the problems of school algebra relating to the transfer from arithmetic to algebra with the problem of teaching algebraic thinking and analyzed the algebraic thinking factors of school algebra, and searched for alternative ways for improving the transfer from arithmetic to algebra and the teaching of early algebra.

• Proceedings of the Acoustical Society of Korea Conference
• /
• spring
• /
• pp.339-342
• /
• 2000

본 논문에서는 DSP와 RISC 마이크로 콘트롤러의 결합으로 구성된 이중 코어 DSP를 이용하여 휴대장치에 적합한 저전력 MPEC-2 계층-III 복호화기의 구조를 제안하고 실시간 시스템을 구현하였다. 제안된 시스템은 디지털 오디오 데이터 처리부와 시스템 제어 정보처리부로 나누어 병렬처리가 가능한 구조이다. 디지털 오디오데이터 처리부에서는 DSP의 강력한 산술연산기능으로 MPEG 복호화 알고리듬을 수행하며 시스템 제어부에서는 마이크로 콘트롤러의 장점인 저가, 저전력의 제어 기능으로 사용자 인터페이스 및 파일 관리, 비트스트림 제어를 담당하도록 구성된다. 입력부에서는 Multi Meadia Card(MMC)를 지원하고, PC와 호환 가능하도록 파일 관리 시스템으로 운용되며 직렬 통신의 데이터 전송과 16비트 해상도 및 최대 48kHz 표본화주파수로 스테레오 출력이 가능하다. 구현된 시스템은 이중 코어를 이용하여 DSP의 연산량 및 동작속도의 감소로 인한 저가, 저전력의 효과로 인해 휴대장치에 적합하다.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.46 no.4
• /
• pp.40-45
• /
• 2009

In This Paper, New Efficient Arithmatic Logic Unit Design for Calculating Error Values of Reed Solomon Decoder is described. Error Values are solved by solving Linear system of Equations, So called Newtonian set of identity equations. Here We Need Galois Multiplier, Adder, Divider on GF($2^8$) field. We prove how the Hardware circuits are improved better than the classical circuits. The method to find error location is not covered here, since many other researchers have already deeply studied it.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.5
• /
• pp.528-535
• /
• 1988

This paper presents a constructing theory of variable arithmetic operation systems for computing multiplications and multiplicative inverse in GF(2**m) based on a modulo operation of degree on elements in Galois fields. The proposed multiplier is composed of a zero element control part, input element conversion part, inversion circuit, and output element conversion part. These systems can reduce reasonable circuit areas due to the common use of input/output element converison parts, and the PLA and module structure provice a variable property capable of convertible uses as arithmetic operation systems over different finite fields. This type of designs gives simple, regular, expandable, and concurrent properties suitable for VLSI implementation. Expecially, the multiplicative inverse circuit proposed here is expected to offer a characteristics of the high operation speed than conventional method.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.3C
• /
• pp.245-249
• /
• 2006

In general, a large number of the memory accesses are required to decode the CAVLC in H.264/AVC. This is a serious problem for applications such as a DMB and videophone services because of the considerable amount of power that is consumed in accessing the memory. In order to overcome this problem, we propose an efficient run_before decoding method, In the proposed method, the memory access is removed by using a FSM with arithmetic operations. The simulation results show that the proposed algorithm does not degrade video quality is not degraded as well as the power is saved.

• The Transactions of the Korea Information Processing Society
• /
• v.2 no.2
• /
• pp.247-253
• /
• 1995

An efficient algorithm for clipping 2D lines on a rectangular window is proposed. It is suitable for displaying images consisted of many lines for it can reduce the number of arithmetic and logical operations. The algorithm is compared with the Cohen-Sutherland algorithm and it was proved to be efficient.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.3
• /
• pp.137-144
• /
• 1990

We describe how single layer perceptrons and new nonsymmetry feedback type neural networks can be implemented by VLSI CMOS technology. The network described provides a flexible tool for evaluation of boolean expressions and arithmetic equations. About 50 CMOS VLSI chips with an architecture based on two neural networks have been designed and me being fabricated by 2-micrometer double metal design rules. These chips have been developed to study the potential of neural network models for the use in character recognition and for a neural compute.