• Journal of the Korea Convergence Society
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• v.12 no.4
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• pp.249-258
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• 2021

Bitcoin prices have been soaring recently as investors flock to cryptocurrency exchanges. The purpose of this study is to predict the Bitcoin price using a deep learning model and analyze whether Bitcoin is profitable through investment strategy. LSTM is utilized as Bitcoin prediction model with nonlinearity and long-term memory and the profitability of MA cross-over strategy with predicted prices as input variables is analyzed. Investment performance of Bitcoin strategy using LSTM forecast prices from 2013 to 2021 showed return improvement of 5.5% and 46% more than market price MA cross-over strategy and benchmark Buy & Hold strategy, respectively. The results of this study, which expanded to recent data, supported the inefficiency of the cryptocurrency market, as did previous studies, and showed the feasibility of using the deep learning model for Bitcoin investors. In future research, it is necessary to develop optimal prediction models and improve the profitability of Bitcoin investment strategies through performance comparison of various deep learning models.

• Journal of Internet Computing and Services
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• v.23 no.5
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• pp.103-110
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• 2022

Botnets have been exploited for a variety of purposes, ranging from monetary demands to national threats, and are one of the most threatening types of attacks in the field of cybersecurity. Botnets emerged as a centralized structure in the early days and then evolved to a P2P structure. Bitcoin is the first online cryptocurrency based on blockchain technology announced by Satoshi Nakamoto in 2008 and is the most widely used cryptocurrency in the world. As the number of Bitcoin users increases, the size of Bitcoin network is also expanding. As a result, a botnet using the Bitcoin network as a C&C channel has emerged, and related research has been recently reported. In this study, we propose an encrypted botnet C&C communication mechanism and technique in the Bitcoin network and validate the proposed method by conducting performance evaluation through various experiments after building it on the Bitcoin testnet. By this research, we want to inform the possibility of botnet threats in the Bitcoin network to researchers.

• The Journal of the Korea Contents Association
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• v.8 no.10
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• pp.37-44
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• 2008

This paper presented a solution to encryption and decryption problem suffering data transmission error for encrypted message transmission. Block cypher algorithms experience avalanche effect that a single bit error in an encrypted message brings substantial error bits after decryption. The proposed fault tolerant scheme addresses this error avalanche effect exploiting a multi-dimensional data array shuffling process and an error correction code. The shuffling process is to simplify the error correction. The shuffling disperses error bits to many data arrays so that each n-bit data block may comprises only one error bit. Thereby, the error correction scheme can easily restore the one bit error in an n-bit data block. This scheme can be extended on larger data blocks.

• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1565-1575
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• 1997

A new encryption algorithm had been proposed as a replacement to the Data Encryption Standard (DES) in [1,2]. It called the Extended DES (EDES) has a key length of 112 bits. The plaintext data consists of 96 bits divided into 3 sub-blocks of 32 bits each. The EDES has a potentially higher resistance to differential cryptanalysis that the DES due to the asymmetric number of f functions performed on each of the 3 sub-blocks and due to the increase of S-boxes from 8 to 16. This paper propose a hardware design for the EDES and its implementation in VLSI. The VLSI chip implements data encryption and decryption in a single hardware unit. With a system clock frequency of 15Mhz the device permits a data conversion rate of about 90Mbit/sec. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols.

• Journal of the Korea Society of Computer and Information
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• v.18 no.7
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• pp.1-10
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• 2013

In this paper, the parallel branch instruction is proposed which executes a branch instruction and the frequently used instruction simultaneously to improve the performance of Thumb-2 instruction set architecture. In the proposed approach, new 32-bit parallel branch instructions are introduced which combine 16-bit branch instruction with each of the frequently used 16-bit LOAD, ADD, MOV, STORE, and SUB instructions, respectively. To provide the encoding space of the new instructions, the register field in less frequently executed instructions is reduced, and the new instructions are encoded by using the saved bits. Experiments show that the proposed approach improves performance by an average of 8.0% when compared to the conventional approach.

• Annual Conference of KIPS
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• 2012.11a
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• pp.68-71
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• 2012

본 논문은 운영 체제(Operating System)에서 수행되는 프로세스(Process)의 가상 주소 공간(Virtual Address Space)을 기존의 단일 가상 주소 공간에서 다중 가상 주소 공간으로 확장시켜서, 하나의 프로세스가 기존보다 더욱 넓은 가상 메모리 영역을 쉽게 사용할 수 있도록 해주는 방안을 제안한다. 최근 컴퓨팅 기기들은 비약적으로 증가한 메모리를 쉽게 사용할 수 있는 수단이 필요하다. 최근 PAE(Physical Address Extension)를 지원하는 32 비트 프로세서나 32 비트 명령어를 같이 지원하는 64비트 프로세서들은 프로세스의 가상 주소 크기보다 더욱 큰 용량의 메모리를 사용할 수 있어서, 한 프로세스가 장착된 메모리의 일부분 밖에 사용할 수 없는 일이 발생한다. 이를 해결하기 위해서 64비트 프로세서의 경우 64-비트 명령어를 사용하지만 이는 프로그램의 명령어 크기나 포인터 변수 크기의 증가로 메모리 사용량을 크게 늘릴 수 있어서 서버 컴퓨터나 데스크탑 PC 와 같이 충분한 양의 메모리를 장착한 시스템에서만 효과적이다. 본 논문에서 제안하는 다중 주소 공간을 지원하는 프로세스는 모바일 및 임베디드 기기와 같이 상대적으로 제한된 용량의 메모리를 지원하는 시스템에 유용할 것으로 기대한다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.15 no.1
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• pp.57-66
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• 2005

SHACAL-2 is a 256-bit block cipher with various key sizes based on the hash function SHA-2. Recently, it was recommended as one of the NESSIE selections. This paper presents differential-linear type attacks on SHACAL-2 with 512-bit keys up to 32 out of its 64 rounds. Our 32-round attack on the 512-bit keys variants is the best efficient attack on this cipher in published literatures.

• The Journal of the Korea Contents Association
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• v.9 no.4
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• pp.189-197
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• 2009

A digital image usually has 8 bits of depth basically representing pixel intensity ranging for [0 255]. These pixel range allow 256 step levels of pixel values in the image. Thus the greyscale value for a given image is an integer. When we carry out interpolation of a given image for resizing we have to round the interpolated value to integer which can result in loss of quality on perceived color values. This paper proposes a new method for recovering this loss of information during interpolation process. By using the proposed method the pixels tend to regain more original values which yields better looking images on resizing.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• The KIPS Transactions:PartC
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• v.12C no.4 s.100
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• pp.465-472
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• 2005

IEEE 802.11 wireless LAN technology is essential for wireless internet, next generation converged network and home network. But, it is certain that user's privacy must be provided to expand the applicable area in IEEE 802.11 WLAN. Recently, WEP and 802.11i security scheme can be used in MAC Layer. But with VPN technology which is applied to WLAN user, it means that suity mechanism is used redundantly. One bit authentication mechanism was already proposed to solve this redundancy. In this paper, we analyze problems of 1-bit Authentication mechanism which are failure of synchronization and waste of packet. And we propose new algorithm which synchronizes sender with receiver, at once, using duplicated-packet-count information. We show that our algorithm improves success probability of packet authentication up to $98\%$ and efficiency of authentication bit stream up to $97\%$.