• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1536-1547
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• 1994

This paper presented the implementation and design of narrowband wireless MODEM for packet transmission. The MODEM consists of transmitter, receiver, and the control unit. The BPSK modulation with narrowband filtering is used. The receiver consists of functional modules such as carrier recovery, bit synchronization, lock detector, etc. We evaluated the performance of packet transmission with three MODEM sets implemented in distributed packet radio network. We confirmed the transmission of packetized data through RS232C port of PC. Also, we presented results of experimental data by using measuring instruments. The implemented MODEM in this paper is expected to be useful for the design of wireless LAN system.

• Proceedings of the Korean Society of Computer Information Conference
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• 2010.07a
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• pp.173-179
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• 2010

Currently, the communication systems are progressing two ways as the wireless and multimedia and these need big transmission capacity then before. In these circumstance, communication services existed as two different service forms which have different rates and characteristics. For example Voice/Video Services accept some errors but transmit on realtime, but Date Services don't need to transmit on realtime but have to retransmit if these have only one bit error. In Voice/Date Integrated traffics, it has big throughput that realtime voice/video data which could have some errors if integrated traffic is increased rapidly have transmission priority, then Data traffics which delay is accepted is sent after that. In this paper, I introduce the calculation method for various traffic when voice/data mixed traffics is transmitted to asynchronous unslotted ALOHA CDMA system proposed and the result is presented. And We can easily theoretical analysis for the system traffic and changing traffic using proposed solution in this paper.

• The KIPS Transactions:PartC
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• v.16C no.1
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• pp.57-64
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• 2009

In order to efficiently provide IP based Wireless Broadband services in Mobile WiMAX, schemes for more efficiently utilizing a limited bandwidth in radio links are needed. Robust Header Compression (ROHC), a standard header compression scheme proposed by IETF, Bi-directional Optimistic (O) mode provides higher compression efficiency and robustness compared with Payload Header Suppression (PHS) which is an optional header compression scheme for mobile WiMAX [1, 2]. However, if consecutive packet losses occur because of a Shadow Region of Mobile WiMAX or bit errors, header decompression failure rate of the ROHC O mode increases due to inconsistency of the compression information between the Compressor and the Decompressor. Therefore, a complementary mechanism is needed. In this paper, we propose an approach for the dynamic adjustment of an optimistic parameter, which has an effect on both the compression efficiency and the robustness, for improving the performance of ROHC O mode. We also analyze the performance of the proposed approach using an OPNET simulator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.3
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• pp.23-32
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• 2001

Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.