• Journal of Broadcast Engineering
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• v.20 no.2
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• pp.257-264
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• 2015

In this paper, Enhanced binary block matching method for Constrained one-bit transform (C1BT) based motion estimation is proposed. Binary motion estimation exploits the Number of non-matched points (NNMP) as a block matching criterion instead of the Sum of Absolute Differences (SAD) for low complex motion estimation. The motion estimation using SAD could use the smaller block for more accurate motion estimation. In this paper the enhanced binary block matching method using smaller motion estimation block for C1BT is proposed to the more accurate binary matching. Experimental results shows that the proposed algorithm has better Peak Signal to Noise Ration (PSNR) results compared with conventional binary transform algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.3C
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• pp.256-262
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• 2002

This paper presents a novel radix-4 modular multiplication algorithm based on the sign estimation technique (3). The sign estimation technique detects the sign of a number represented in the form of a carry-sum pair. It can be implemented with 5-bit carry look-ahead adder. The hardware speed of the cryptosystem is dependent on the performance modular multiplication of large numbers. Our algorithm requires only (n/2+3) clock cycle for n bit modulus in performing modular multiplication. Our algorithm out-performs existing algorithm in terms of required clock cycles by a half, It is efficient for modular exponentiation with large modulus used in RSA cryptosystem. Also, we use high-speed adder (7) instead of CPA (Carry Propagation Adder) for modular multiplication hardware performance in fecal stage of CSA (Carry Save Adder) output. We apply RL (Right-and-Left) binary method for modular exponentiation because the number of clock cycles required to complete the modular exponentiation takes n cycles. Thus, One 1024-bit RSA operation can be done after n(n/2+3) clock cycles.

• Journal of The Korean Association of Information Education
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• v.12 no.4
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• pp.405-415
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• 2008

In the existing curriculum of the Elementary Computer Education, it is hard to improve the CPS(Creative Problem Solving) skill and logical thought since the 7th national curriculum emphasizes application programs and CAI softwares. To complement this drawback, it is required to teach the principal of the computer science but there is not many researches for what problems of teaching computer science exist and what the response of students are. Thus, we carried out a research to know whether the students of elementary school can understand principal of computer science in the field of subject matter education. We found that the students can learn the principle of Saving Bitmap Image if the class level is adjusted properly.

• Journal of Korea Multimedia Society
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• v.9 no.10
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• pp.1257-1265
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• 2006

As XML is increasingly used, the need of researches which are related with XML in various fields is also augmented. Many XML document management systems have been actively developed especially for the storage, processing and retrieval of XML documents. The BitCube is a three dimensional bitmap index system that could be manipulated efficiently and improves the performance of document retrieval. However, the site of index is increase rapidly, when a new bit is added to the axis. This problem is caused by its three dimensional memory structure with document, path and word. We suggest a path combining strategy of XML documents in this paper to solve the problem of BitCube that mentioned above. To reduce the size of index, our approach combines sibling nodes that has same ancestor paths, and transforms word axis into value axis. The method reduces the size of index, when the system com poses the three dimensional bitmap index. It also improves the speed of retrieving, and takes efficiency in storage space.

• The KIPS Transactions:PartD
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• v.11D no.3
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• pp.717-730
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• 2004

Recently. many researches on the personalization of a web-site have been actively made. The web personalization predicts the sets of the most interesting URLs for each user through data mining approaches such as clustering techniques. Most existing methods using clustering techniques represented the web transactions as bit vectors that represent whether users visit a certain WRL or not to cluster web transactions. The similarity of the web transactions was decided according to the match degree of bit vectors. However, since the existing methods consider only whether users visit a certain URL or not, users' interestingness on the URL is excluded from clustering web transactions. That is, it is possible that the web transactions with different visit proposes or inclinations are classified into the same group. In this paper. we propose an enhanced transaction modeling with interestingness weight to solve such problems and a new similarity measuring method that exploits the proposed transaction modeling. It is shown through performance evaluation that our similarity measuring method improves the accuracy of the web transaction clustering over the existing method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.29-42
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• 1990

In this paper, We use the APL as IDL when simulation a 16-bit SIP. It was possible for IDL to represent and describe a structure of a H/W which other HDL have not. Because We partitioned whole system to various modules when desingning processor, We adpoted a direct decoding method. A designed each modules are executed according to 12-bit control word was inputed through experimental framework, Which were composed to symbolized instructions. In here, By setting instruction codes of the SIP using binary code, We composed instruction format and assembler instruction, and verified the SIP behaviour that try to implement by entering a presented instruction set through experimental framework. In a presented SIP, Because inputing program are a symbolized language, Designer and user will easily understand behaviour of system. Especially, Because we can immediatly specify a unit function within SIP, We will use variously and easily the library cell.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.45-52
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• 2005

A systolic array formed by interconnecting a set of identical data-processing cells in a uniform manner is a combination of an algorithm and a circuit that implements it, and is closely related conceptually to arithmetic pipeline. High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The structure of systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a scalable bit-level super-systolic amy which can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture. This architecture is focused on highly regular computational structures that avoids the need for a large number of global interconnection required in general VLSI implementation. A bit-level super-systolic FIR filter is selected as an example of bit-level super-systolic array. The derived bit-level super-systolic FIR filter has been modeled and simulated in RT level using VHDL, then synthesized using Synopsys Design Compiler based on Hynix $0.35{\mu}m$ cell library. Compared conventional word-level systolic array, the newly proposed bit-level super-systolic arrays are efficient when it comes to area and throughput.

• Journal of KIISE:Information Networking
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• v.30 no.2
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• pp.282-292
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• 2003

This paper proposes an efficient data structure for forwarding IPv4 and IPv6 packets at the gigabit speed in backbone routers. The LPM(Longest Prefix Matching) search becomes a bottleneck of routers' performance since the LPM complexity grows in proportion to the forwarding table size and the address length. To speed up the forwarding process, this paper introduces a data structure named BMT(Bit-Map Tie) to minimize the frequent main memory accesses. All the necessary search computations in BMT are done over a small index table stored at cache. To build the small index table from the tie representation of the forwarding table, BMT represents a link pointer to the child node and a node pointer to the corresponding entry in the forwarding table with one bit respectively. To improve the poor performance of the conventional tries when their height becomes higher due to the increase of the address length, BMT adopts a binary search algorithm for determining the appropriate level of tries to start. The simulation experiments show that BMT compacts the IPv4 backbone routers' forwarding table into a small one less than 512-kbyte and achieves the average speed of 250ns/packet on Pentium II processors, which is almost the same performance as the fastest conventional lookup algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• Journal of Korea Multimedia Society
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• v.10 no.2
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• pp.269-277
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• 2007

Network clustering has been proposed to provide that sensor nodes minimize energy and maximize a network lifetime by configuring clusters, Although dynamic clustering brings extra overhead like as head changing, head advertisement, it may diminish the gain in energy consumption to report attribute tasks by using cluster heads. Therefore, this paper proposes a new routing algorithm which configures cluster to reduce the number of messages when establishing paths and reports to the sink by way of cluster heads when responding sens ing tasks. All sensor nodes only broadcast bitmap once and maintain a bitmap table expressed by bits, allowing them to reduce node energy and to prolong the network lifetime. After broadcasting, each node only updates the bitmap without propagation when the adjacent nodes broad cast same query messages, This mechanism makes nodes to have abundant paths. By modifying the query which requests sensing tasks, the size of cluster is designed dynamically, We try to divide cluster by considering the number of nodes. Then, all nodes in a certain cluster must report to the sub- sink node, The proposed routing protocol finds easily an appropriate path to report tasks and reduces the number of required messages for the routing establishment, which sensor nodes minimize energy and maximize a network lifetime.