• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.11-16
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• 2005

This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.3
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• pp.661-669
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• 2000

DS-CDMA downlink distinguishes actual user by orthogonal spreading codes ,but its orthogonality may be lost by the multiple access interference(MAI) caused by the multipath channel. Therefore in this paper, we proposed the single-user receiver, which use linear channel equalizer to eliminate the interference due to multipath channel and to recover orthogonality and then use code-matched filter to detect transmitted data. Unlike existing research, which mainly assumed ideal channel information, we use pilot channel assisted methods that is a kind of transmission of a parallel reference method to estimate the channel coefficients. Especially we use guard symbols which are inserted periodically to estimate channel coefficients exactly without interference from user signal. The results show that we accepted an approximately ideal channel information and achieved excellent performance improvement using proposed receiver compared with the conventional receiver especially user populations are high.

• Database Research
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• v.34 no.3
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• pp.14-27
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• 2018

Recently, to alleviate the memory bottleneck problme occurred in Symmetric Multiprocessing (SMP) architecture, Non-Uniform Memory Access (NUMA) architecture was proposed. In addition, since an aggregation operator is an important operator providing properties and summary of data, the efficiency of the aggregation operator is crucial to overall performance of a system. Thus, in this paper, we propose an efficient aggregation processing technique on NUMA architecture. Our proposed technique consists of partition phase and merge phase. In the partition phase, the target relation is partitioned into several partial relations according to grouping attribute. Thus, since each thread can process aggregation operator on partial relation independently, we prevent the remote memory access during the merge phase. Furthermore, at the merge phase, we improve the performance of the aggregation processing by letting each thread compute aggregation with a local hash table as well as avoiding lock contention to merge aggregation results generated by all threads into one.

• The KIPS Transactions:PartC
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• v.13C no.1 s.104
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• pp.83-94
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• 2006

This paper describes ATM cell encipherment method using Rijndael Algorithm adopted as an AES(Advanced Encryption Standard) by NIST in 2001. ISO 9160 describes the requirement of physical layer data processing in encryption/decryption. For the description of ATM cell encipherment method, we implemented ATM data encipherment equipment which satisfies the requirements of ISO 9160, and verified the encipherment/decipherment processing at ATM STM-1 rate(155.52Mbps). The DES algorithm can process data in the block size of 64 bits and its key length is 64 bits, but the Rijndael algorithm can process data in the block size of 128 bits and the key length of 128, 192, or 256 bits selectively. So it is more flexible in high bit rate data processing and stronger in encription strength than DES. For tile real time encryption of high bit rate data stream. Rijndael algorithm was implemented in FPGA in this experiment. The boundary of serial UNI cell was detected by the CRC method, and in the case of user data cell the payload of 48 octets (384 bits) is converted in parallel and transferred to 3 Rijndael encipherment module in the block size of 128 bits individually. After completion of encryption, the header stored in buffer is attached to the enciphered payload and retransmitted in the format of cell. At the receiving end, the boundary of ceil is detected by the CRC method and the payload type is decided. n the payload type is the user data cell, the payload of the cell is transferred to the 3-Rijndael decryption module in the block sire of 128 bits for decryption of data. And in the case of maintenance cell, the payload is extracted without decryption processing.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.51-62
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• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.105-113
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• 2013

RAID systems have been widely used by connecting several disks in parallel structure. to resolve the delay and bottleneck of data I/O. Recently, SSD based RAID systems are emerging since SSDs have better I/O performance than HDD. However, endurance and power consumption problems due to frequent write operation in SSD based RAID system should be resolved. In this paper, we propose a de-duplication method of parity disk in SSD based RAID system with expensive update cost. The proposed method segments chunk of parity data into small pieces and removes duplicate data, therefore, it can reduce wear-leveling and power consumption by decreasing write operation for duplicated parity data. Experimental results show that bit update rate of the proposed method is 16% in total disk, 31% in parity disk less than that of existing method in RAID-6 system using EVENODD erasure code, and the power consumption of the proposed method is 30% less than that of existing method. Besides the proposed method is 12% in total disk, 32% in parity disk less than that of existing method in RAID-5 system, and the power consumption of the proposed method is 36% less than that of existing method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.25-32
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• 2011

Networks-on-chip (NoC) is emerging as a key technology to overcome severe bus traffics in ever-increasing complexity of the Multiprocessor systems-on-chip (MPSoC); however traditional electrical interconnection based NoC architecture would be faced with technical limits of bandwidth and power consumptions in the near future. In order to cope with these problems, a hybrid optical NoC architecture which use both electrical interconnects and optical interconnects together, has been widely investigated. In the hybrid optical NoCs, wormhole switching and simple deterministic X-Y routing are used for the electrical interconnections which is responsible for the setup of routing path and optical router to transmit optical data through optical interconnects. Optical NoC uses circuit switching method to send payload data by preset paths and routers. However, conventional hybrid optical NoC has a drawback that concurrent transmissions are not allowed. Therefore, performance improvement is limited. In this paper, we propose a new routing algorithm that uses circuit switching and adaptive algorithm for the electrical interconnections to transmit data using multiple paths simultaneously. We also propose an efficient method to prevent livelock problems. Experimental results show up to 60% throughput improvement compared to a hybrid optical NoC and 65% power reduction compared to an electrical NoC.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.188-198
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• 2013

In order to increase its performance, NAND flash memory-based storage is composed of data buses that are shared by a number of flash memories and uses a parallel technique that can carry out multiple flash memory operations simultaneously. Since the storage performance is strongly influenced by the performance of each data bus, it is important to improve the utilization of the bus by ensuring effective scheduling of operations by the storage controller. However, this is difficult because of dynamic changes in buses due to the unique characteristics of each operation with different timing, cost, and usage by each bus. Furthermore, the scheduling technique for increasing bus utilization may cause unanticipated operation delay and wastage of storage resource. In this study, we suggest various dynamic operation scheduling techniques that consider data bus performance and storage resource efficiency. The proposed techniques divide each operation into three different stages and schedule each stage depending on the characteristics of the operation and the dynamic status of the data bus. We applied the suggested techniques to the controller and verified them on the FPGA platform, and found that program operation decreased by 1.9% in comparison to that achieved by a static scheduling technique, and bus utilization and throughput was approximately 4-7% and 4-19% higher, respectively.

• Proceedings of the Korea Society for Simulation Conference
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• 1997.04a
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• pp.65-65
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• 1997

가입자가 B-ISDN(Broadband Integrated Services Digital Network) 서비스에 대한 shb은 수준의 품질 및 안정적인 서비스 제공을 요구함에 따라, 이러한 서비스를 제공하기 위한 ATM (Asynchronous Transfer Mode) 교환기에 대한 신뢰성 설계의 중요성은 증가하 고 있다. 교환기의 중요한 신뢰성 성능 척도 중의 하나인 연결 절단율 (Cutoff connection rate)은 총 연결시간 동안 절단된 연결수로 정의되며, 연결 절단은 호 설정 (Call setup) 단 계를 지나 서비스 중인 연결이 사용자의 요구가 아닌 시스템의 고장으로 종료될 때 발생한 다. 연결 절단율 추정 문제는 기존의 신뢰도 또는 가용도 예측을 위한 시뮬레이션과는 달리 시스템 구성 유니트들의 고장율, 수리율, 그리고 요구된 연결의 트래픽 특성 부분이 혼합된 문제이다. 따라서, B-ISDN 서비스의 중요한 특징인 다양한 트래픽 특성과 시스템의 구성 (Configuration)을 고려하여 연결 절단율을 해석적인 방법을 통하여 추정하는 데네는 어려 움이 있으며 시뮬레이션에 의한 방법이 적절하다. 본 고에서는 B-ISDN 서비스의 트래픽 특 성과 ATM 교환기의 시스템 구성 및 신뢰도 데이터로부터 시스템의 연결 절단율을 추정하 기 위한 시뮬레이터의 기능 및 구조, 시뮬레이션 수행 결과 등을 제시한다. 시뮬레이터는 AweSim 시뮬레이션과 CUser Written Code를 사용하여 개발하였다. 시뮬레이터의 구성 모듈은 크게 호 도착 모듈, 연결 제어 및 자원 할당 모듈, 유니트 고장 및 수리 모듈, 통계 량 수집 모듈 등으로 구성된다. 개발된 시뮬레이터는 B-ISDN 트래픽 파라메터와 연결 절단 율의 상호 관계 규명 및 시스템 설계 대안 (Design alternatives)에 대한 비교/평가에 활용 된다., 수중생물의 경우는 특히 수온, 수량 영양원등이다.(중략). 본 연구의 접근방법으로는 ASRS의 개념적인 Reference Model을 수립하고 이 Reference Model에 대한 Formal Model로 DEVS(Discrete Event System Specification)을 이용하여 시스템을 Modeling하였다. 이의 Computer Simulation을 위하여 DEVS형식론 환경에서의 Simulation Language인 DEVSim ++ⓒ를 이용하여 시스템을 구현하였다.. 실형 결과로는 먼저 선형 상미분방정식의 예로 mass-damper-spring system, 비선형 상미분방정식의 예로는 van der Pol 방정식, 연립 상미분방정식의 예로는 mixing tank problem 등을 보였으며, 그의 공학에서 일어나는 여러 가지 문제들도 다루었다.화물에 대한 방어력이 증가되어 나타난 결과로 여겨지며, 또한 혈청중의 ALT, ALP 및 LDH활성을 유의성있게 감소시키므로서 감잎 phenolic compounds가 에탄올에 의한 간세포 손상에 대한 해독 및 보호작용이 있는 것으로 사료된다.반적으로 홍삼 제조시 내공의 발생은 제조공정에서 나타나는 경우가 많으며, 내백의 경우는 홍삼으로 가공되면서 발생하는 경우가 있고, 인삼이 성장될 때 부분적인 영양상태의 불충분이나 기후 등에 따른 영향을 받을 수 있기 때문에 앞으로 이에 대한 많은 연구가 이루어져야할 것으로 판단된다.태에도 불구하고 [-wh]의미의 겹의문사는 병렬적 관계의 합성어가 아니라 내부구조를 지니지 않은 단순한 단어(minimal $X^{0}$ elements)로 가정한다. 즉, [+wh] 의미의 겹의문사는 동일한 구성요 소를 지닌 병렬적 합성어([$[W1]_{XO-}$ $[W1]_{XO}$ ]$_{XO}$

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.3
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• pp.401-410
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• 2023

In this paper, we propose optimization methods for implementing SPARKLE, one of the NIST LWC finalists, on a 64-bit ARMv8 processor. The proposed methods consist of two approaches: an implementation using ARM A64 instructions and another using NEON ASIMD instructions. The A64-based implementation is optimized by performing register scheduling to efficiently utilize the available registers on the ARMv8 architecture. By utilizing the optimized A64-based implementation, we can achieve speeds that are 1.69 to 1.81 times faster than the C reference implementation on a Raspberry Pi 4B. The ASIMD-based implementation, on the other hand, optimizes data by parallelizing the ARX-boxes to perform more than three of them concurrently through a single vector instruction. While the general speed of the optimized ASIMD-based implementation is lower than that of the A64-based implementation, it only slows down by 1.2 times compared to the 2.1 times slowdown observed in the A64-based implementation as the block size increases from SPARKLE256 to SPARKLE512. This is an advantage of the ASIMD-based implementation. Therefore, the ASIMD-based implementation is more efficient for SPARKLE variant block cipher or permutation designs with larger block sizes than the original SPARKLE, making it a useful resource.