• Title/Summary/Keyword: 비병렬 데이터

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Effectiveness of 32-element Surface Coil Array for Accelerated Volume-Targeted Breath-Hold Coronary MRA (체적 지향형 호흡정지 자기공명 조영술의 가속화에 대한 32채널 코일 어레이의 효용성)

  • Lee, Hyun-Yeol;Suh, Jin-Suck;Park, Jae-Seok
    • Investigative Magnetic Resonance Imaging
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    • v.13 no.2
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    • pp.137-145
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    • 2009
  • Purpose : To compare 12 and 32-element surface coil arrays for highly accelerated coronary magnetic resonance angiography (MRA) using parallel imaging. Materials and Methods : Steady state free precession coronary MRA was performed in 5 healthy volunteers at 1.5 T whole body MR scanner using both 12 and 32-element surface coil arrays. Left anterior descending and right coronary artery data sets were acquired for each volunteer. Data sets were sub-sampled for parallel imaging using reduction factors from 1 to 6. Mean geometry factor (g-factor), maximum g-factor, and artifact level were calculated for each of the two coil arrays. Results : Over all reduction factors, the mean and maximum g-factors and artifact level were significantly reduced using the 32-element array compared to the 12element array (P << 0.1). The mean g-factor was sensitive to the imaging orientations of coronary arteries while the maximum g-factor and artifact level were independent of orientation. Conclusion : The 32-element surface coil array significantly improves artifact and noise suppression for highly accelerated coronary MRA using parallel imaging. The increased acceleration factors made feasible with the 32-element array offer the potential to enhance spatial resolution or increase volumetric coverage for 3D coronary MRA.

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DFT-spread OFDM Communication System for the Power Efficiency and Nonlinear Distortion in Underwater Communication (수중통신에서 비선형 왜곡과 전력효율을 위한 DFT-spread OFDM 통신 시스템)

  • Lee, Woo-Min;Ryn, Heung-Gyoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.8A
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    • pp.777-784
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    • 2010
  • Recently, the necessity of underwater communication and demand for transmitting and receiving various data such as voice or high resolution image data are increasing as well. The performance of underwater acoustic communication system is influenced by characteristics of the underwater communication channels. Especially, ISI(inter symbol interference) occurs because of delay spread according to multi-path and communication performance is degraded. In this paper, we study the OFDM technique to overcome the delay spread in underwater channel and by using CP, we compensate for delay spread. But PAPR which OFDM system has problem is very high. Therefore, we use DFT-spread OFDM method to avoid nonlinear distortion by high PAPR and to improve efficiency of amplifier. DFT-spread OFDM technique obtains high PAPR reduction effect because of each parallel data loads to all subcarrier by DFT spread processing before IFFT. In this paper, we show performance about delay spread through OFDM system and verify method that DFT spread OFDM is more suitable than OFDM for underwater communication. And we analyze performance according to two subcarrier mapping methods(Interleaved, Localized). Through the simulation results, performance of DFT spread OFDM is better about 5~6dB at $10^{-4}$ than OFDM. When compared to BER according to subcarrier mapping, Interleaved method is better about 3.5dB at $10^{-4}$ than Localized method.

Design and Implementation of an Efficient Web Services Data Processing Using Hadoop-Based Big Data Processing Technique (하둡 기반 빅 데이터 기법을 이용한 웹 서비스 데이터 처리 설계 및 구현)

  • Kim, Hyun-Joo
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.1
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    • pp.726-734
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    • 2015
  • Relational databases used by structuralizing data are the most widely used in data management at present. However, in relational databases, service becomes slower as the amount of data increases because of constraints in the reading and writing operations to save or query data. Furthermore, when a new task is added, the database grows and, consequently, requires additional infrastructure, such as parallel configuration of hardware, CPU, memory, and network, to support smooth operation. In this paper, in order to improve the web information services that are slowing down due to increase of data in the relational databases, we implemented a model to extract a large amount of data quickly and safely for users by processing Hadoop Distributed File System (HDFS) files after sending data to HDFSs and unifying and reconstructing the data. We implemented our model in a Web-based civil affairs system that stores image files, which is irregular data processing. Our proposed system's data processing was found to be 0.4 sec faster than that of a relational database system. Thus, we found that it is possible to support Web information services with a Hadoop-based big data processing technique in order to process a large amount of data, as in conventional relational databases. Furthermore, since Hadoop is open source, our model has the advantage of reducing software costs. The proposed system is expected to be used as a model for Web services that provide fast information processing for organizations that require efficient processing of big data because of the increase in the size of conventional relational databases.

Adaptive Pipeline Architecture for an Asynchronous Embedded Processor (비동기식 임베디드 프로세서를 위한 적응형 파이프라인 구조)

  • Lee, Seung-Sook;Lee, Je-Hoon;Lim, Young-Il;Cho, Kyoung-Rok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.1
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    • pp.51-58
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    • 2007
  • This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design

Bias and Gate-Length Dependent Data Extraction of Substrate Circuit Parameters for Deep Submicron MOSFETs (Deep Submicron MOSFET 기판회로 파라미터의 바이어스 및 게이트 길이 종속 데이터 추출)

  • Lee Yongtaek;Choi Munsung;Ku Janam;Lee Seonghearn
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.12
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    • pp.27-34
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    • 2004
  • The study on the RF substrate circuit is necessary to model RF output characteristics of deep submicron MOSFETs below 0.2$\mum$ gate length that have bun commercialized by the recent development of Si submicron process. In this paper, direct extraction methods are developed to apply for a simple substrate resistance model as well as another substrate model with connecting resistance and capacitance in parallel. Using these extraction methods, better agreement with measured Y22-parameter up to 30 GHz is achieved for 0.15$\mum$ CMOS device by using the parallel RC substrate model rather than the simple resistance one, demonstrating the RF accuracy of the parallel model and extraction technique. Using this model, bias and gate length dependent curves of substrate parameters in the RF region are obtained by increasing drain voltage of 0 to 1.2V at deep submicron devices with various gate lengths of 0.11 to 0.5㎛ These new extraction data will greatly contribute to developing a scalable RF nonlinear substrate model.

Efficient Collaboration Method Between CPU and GPU for Generating All Possible Cases in Combination (조합에서 모든 경우의 수를 만들기 위한 CPU와 GPU의 효율적 협업 방법)

  • Son, Ki-Bong;Son, Min-Young;Kim, Young-Hak
    • KIPS Transactions on Computer and Communication Systems
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    • v.7 no.9
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    • pp.219-226
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    • 2018
  • One of the systematic ways to generate the number of all cases is a combination to construct a combination tree, and its time complexity is O($2^n$). A combination tree is used for various purposes such as the graph homogeneity problem, the initial model for calculating frequent item sets, and so on. However, algorithms that must search the number of all cases of a combination are difficult to use realistically due to high time complexity. Nevertheless, as the amount of data becomes large and various studies are being carried out to utilize the data, the number of cases of searching all cases is increasing. Recently, as the GPU environment becomes popular and can be easily accessed, various attempts have been made to reduce time by parallelizing algorithms having high time complexity in a serial environment. Because the method of generating the number of all cases in combination is sequential and the size of sub-task is biased, it is not suitable for parallel implementation. The efficiency of parallel algorithms can be maximized when all threads have tasks with similar size. In this paper, we propose a method to efficiently collaborate between CPU and GPU to parallelize the problem of finding the number of all cases. In order to evaluate the performance of the proposed algorithm, we analyze the time complexity in the theoretical aspect, and compare the experimental time of the proposed algorithm with other algorithms in CPU and GPU environment. Experimental results show that the proposed CPU and GPU collaboration algorithm maintains a balance between the execution time of the CPU and GPU compared to the previous algorithms, and the execution time is improved remarkable as the number of elements increases.

Confidence Value based Large Scale OWL Horst Ontology Reasoning (신뢰 값 기반의 대용량 OWL Horst 온톨로지 추론)

  • Lee, Wan-Gon;Park, Hyun-Kyu;Jagvaral, Batselem;Park, Young-Tack
    • Journal of KIISE
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    • v.43 no.5
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    • pp.553-561
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    • 2016
  • Several machine learning techniques are able to automatically populate ontology data from web sources. Also the interest for large scale ontology reasoning is increasing. However, there is a problem leading to the speculative result to imply uncertainties. Hence, there is a need to consider the reliability problems of various data obtained from the web. Currently, large scale ontology reasoning methods based on the trust value is required because the inference-based reliability of quantitative ontology is insufficient. In this study, we proposed a large scale OWL Horst reasoning method based on a confidence value using spark, a distributed in-memory framework. It describes a method for integrating the confidence value of duplicated data. In addition, it explains a distributed parallel heuristic algorithm to solve the problem of degrading the performance of the inference. In order to evaluate the performance of reasoning methods based on the confidence value, the experiment was conducted using LUBM3000. The experiment results showed that our approach could perform reasoning twice faster than existing reasoning systems like WebPIE.

Design of Systolic Array for High Speed Processing of Block Matching Motion Estimation Algorithm (블록 정합 움직임추정 알고리즘의 고속처리를 위한 시스토릭 어레이의 설계)

  • 추봉조;김혁진;이수진
    • Journal of the Korea Society of Computer and Information
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    • v.3 no.2
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    • pp.119-124
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    • 1998
  • Block Matching Motion Estimation(BMME) Algorithm is demands a very large amount of computing power and have been proposed many fast algorithms. These algorithms are many problem that larger size of VLSI scale due to non-localized search block data and problem of non-reuse of input data for each processing step. In this paper, we designed systolic arry of high processing capacity, constraints input output pin size and reuse of input data for small VLSI size. The proposed systolic array is optimized memory access time because of iterative reuse of input data on search block and become independent of problem size due to increase of algorithm's parallelism and total processing elements connection is localized spatial and temporal. The designed systolic array is reduced O(N6) time complexity to O(N3) on moving vector and has O(N) input/output pin size.

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Enhancing the performance of taxi application based on in-memory data grid technology (In-memory data grid 기술을 활용한 택시 애플리케이션 성능 향상 기법 연구)

  • Choi, Chi-Hwan;Kim, Jin-Hyuk;Park, Min-Kyu;Kwon, Kaaen;Jung, Seung-Hyun;Nazareno, Franco;Cho, Wan-Sup
    • Journal of the Korean Data and Information Science Society
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    • v.26 no.5
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    • pp.1035-1045
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    • 2015
  • Recent studies in Big Data Analysis are showing promising results, utilizing the main memory for rapid data processing. In-memory computing technology can be highly advantageous when used with high-performing servers having tens of gigabytes of RAM with multi-core processors. The constraint in network in these infrastructure can be lessen by combining in-memory technology with distributed parallel processing. This paper discusses the research in the aforementioned concept applying to a test taxi hailing application without disregard to its underlying RDBMS structure. The application of IMDG technology in the application's backend API without restructuring the database schema yields 6 to 9 times increase in performance in data processing and throughput. Specifically, the change in throughput is very small even with increase in data load processing.

Performance of Network Coding with Best Relay Selection in Fading Channels (페이딩 채널에서 최선 릴레이 선택을 갖는 네트워크 코딩의 성능)

  • Kim, Nam-Soo
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.13 no.4
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    • pp.193-200
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    • 2013
  • Recently, network coding has been actively studied to increase the spectral efficiency of two-way relay wireless channels such as cellular systems as well as broadcasting systems. In this paper, we derive the average transmission capacity and the outage probability of a network coding system, which utilizes two-way data transmission via the best relay rather than multiple relays. Since the data unbalance between the forward and the reverse link in two-way communication systems exists, we include the asymmetric link as well as the symmetric link in the analysis. It is noticed that the space diversity gain increases as the increase of the number of relays. Also we obtain 11.4 dB signal-to-noise ratio (SNR) gain with 9 relays compared to that with single relay in symmetrical link at the given conditions. In asymmetrical links, we denotes that the outage probability is more sensitive to the number of relays rather than data unbalance between the links.