• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.3 s.303
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• pp.53-62
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• 2005

In the decoding process of interframe Wavelet coding, the Wavelet transform requires huge computational complexity. Since the decoder may need to be used in various devices such as PDAs, notebooks, or PC, the decoder's complexity should be adapted to the processor's computational power. So, it is natural that the low complexity codec is also required for scalable video coding. In this paper, we develop a method of controlling and lowering the complexity of the spatial Wavelet transform while sustaining the same coding efficiency as the conventional spatial Wavelet transform. In addition, the proposed method may alleviate the ringing effect for slowly changing image sequences.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.6
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• pp.545-552
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• 2016

As a future key industry, digital signage is being noticed that provides various type of contents and message through a digital display. In particular, korean digital signage industry gets a favorable evaluation for the high level of digital display industry and wired and wireless networking infrastructure. This paper discusses on not only the current status of digital signage in terms of the overall development and standardization, but the very recent technologies such as the ultra-high definition video and human perception that can be applied for future digital signage. Then, this paper concludes by deriving the problems with the current digital signage industry and presenting solutions for future vitalizations of digital signage.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.11a
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• pp.128-130
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• 2013

양안식 3DTV 비디오의 효율적인 압축을 위해 다양한 기술들이 연구되었으며, 그 중 좌우영상으로 상이한 해상도의 영상을 사용하는 비대칭 양안식 영상은 인간의 시각시스템이 상이한 해상도의 양안식 양상을 높은 쪽 영상의 품질에 가깝게 인지하는 특성을 이용한 대표적인 비트레이트를 절감 방식이다. 이에 다양한 연구에서 좌우해상도 차이에 따른 화질 저하 정도를 측정하려는 시도가 이루어졌으나, 기존 연구에서는 적정 시청거리를 고려하지 않고 좌우 영상의 크기만을 고려하여 실험하였으며 따라서 각 연구별로 상이한 실험 결과가 도출되었다. 본 연구에서는 인간의 시각 시스템을 고려하여 적정 시청거리를 계산하고, 이에 따라 좌우영상 비율 별 화질평가를 수행하였다. 특히 본 연구에서는 좌영상을 IID급 방송콘텐츠로 가정하고, 우영상을 모바일 방송콘텐츠로 가정함으로써, 실험 결과의 방송 서비스 활용가능성을 높였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.193-198
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• 1999

In the 21th century, everyone feels that the multimedia system is close at hand in real life due to the rapid advance of the computer processing ability and high speed and high guality of communication services. Also the limited frequencies resource will be optimized due to rapid advances in digital video technology which is believed superior to analogue technology in information engineering. MEPG-2 has been introduced for broadcasting use such as digital TV Thus it features the high-definition and hyper-low bit rate. But, because of much throughput it has been implemented by high-priced private ASIC chip and is not in general use yet. But in this research, noticing the rapid enhancement of PC processor performance comparing with the price. MPEG-2 was developed by real time software MPEG-2 had been known impossible to implement with S/W, but the research proved the possibility of the S/W implementation and below are the pictures also in the research was improved 'Motion Vector and Compensation' Algorithm which requires the most operations and UT was made possible real time process. Multimedia Info Society has settled and accompanied by the rapid advance of image-processing technology and lots of standards.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.1107-1111
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• 2005

The DVR system realization with watermarking and MPEG-4 for real time processing speed improvement is presented in this paper. For the real time processing the system is used the DSP processor, Quick DMA for data transmission, watermarking for security and MPEG-4 compression for facility. The algorithms are that the operational structure has the internal memory of processor, and the optimal realization is suitable to form the DSP processor structure r processed for the iterative operations. The experimental result shows the real time processing is improved 12% over for the D1 image in comparison with the other system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9A
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• pp.868-873
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• 2010

H.264/AVC video compression standard has been adopted for DMB, digital TV and various next generation broadcasting, communication and consumer electronics applications, and modern DVR system is also based on H.264/AVC standard. Although PC-based DVRs use PCI bus for main interface typically, H.264/AVC codec for SOCs use AHB bus for host interface. In this paper, we present an implementation of PCI to AHB interface module for H.264/AVC codec to efficiently communicate with a PC and experimental results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1279-1284
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• 2009

With the advance of multimedia technology, multimedia sharing among multiple devices has become the main issue. This allows users to expect the peer-to-peer distribution of unprotected and protected contents over public network. Inevitably, this situation has caused an incredible piracy activity and Web sites have begun to provide copyrighted A/V data for free. In order to, protect the contents from illegal attacks and distribution, digital right management (DRM) is required. In this paper, we present the minimal cost scrambling scheme for securing the copyrighted multimedia using the data encryption standard (DES) encryption technique. Experimental results indicate that the proposed scrambling techniques achieve a very good compromise between several desirable properties such as speed, security, and file size.

• Journal of Korea Multimedia Society
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• v.20 no.5
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• pp.731-739
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• 2017

Distributed compressed video sensing (DCVS) is a framework that integrates both compressed sensing and distributed video coding characteristics to achieve a low complexity video sampling. In DCVS schemes, motion estimation & motion compensation is employed at the decoder side, similarly to distributed video coding (DVC), for a low-complex encoder. However, since a simple BCS-SPL algorithm is applied to a residual arising from motion estimation and compensation in conventional MC-BCS-SPL (motion compensated block compressed sensing with smoothed projected Landweber) scheme, the reconstructed visual qualities are severly degraded in Wyner-Ziv (WZ) frames. Furthermore, the scheme takes lots of iteration to reconstruct WZ frames. In this paper, the conventional MC-BCS-SPL algorithm is improved to be operated in more effective way in WZ frames. That is, first, the proposed algorithm calculates a correlation coefficient between two reference key frames and, then, by selecting adaptively the reference frame, the residual reconstruction in pixel domain is performed to the conventional BCS-SPL scheme. Experimental results show that the proposed algorithm achieves significantly better visual qualities than conventional MC-BCS-SPL algorithm, while resulting in the significant reduction of the decoding time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.766-772
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• 2007

H.264/AVC is a new international standard for the compression of video images, in which a deblocking filter has been adopted to remove blocking artifacts. This paper proposes an efficient architecture of deblocking filter in H.264/AVC. By making good use of data dependence between neighboring $4{\times}4$ blocks, the memory size is reduced and the throughput of the deblocking filter processing is increased. Compared to the conventional deblocking filters, the proposed architecture enhances the performance of deblocking filter processing from 1.75 to 4.23 times. Hence the proposed architecture is able to perform real-time deblocking of high-resolution($2048{\times}1024$) video applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1605-1614
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• 2008

This paper proposed a new VLSI architecture of motion estimation (ME) and compensation (MC) for efficient video compression and implemented it to hardware. ME is generally calculated using SAD result. So we proposed a new arithmetic method for SAD. The proposed SAD calculation method increases arithmetic efficiency and decreases external memory usage. Finally it increases performance of ME/MC. The proposed ME/MC hardware was implemented to ASIC with TSMC 90nm HVT CMOS library. The implemented hardware occupies about 330K gates and stably operates the clock frequency of 143MHz.