• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.82-90
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• 2002

BDD have become widely used for various CAD applications because Boolean functions can be represented uniquely and compactly by using BDD. The size of the BDD representation for a function is very sensitive to the choice of orderings on the input variable. Therefore, it is very important to find a good variable ordering which minimize the size of the BDD. Since finding an optimal ordering is NP-complete, several heuristic algorithms have been proposed to find good variable orderings. In this paper, we propose a variable ordering algorithm, Faster-${\mu}$0, based on the ${\mu}$0(microcanonical optimization). In the Faster-${\mu}$0 algorithm, the initialization phase is replaced with a shifting phase to produce better solutions in a fast local search. We find values for algorithm parameters experimentally and the proposed algorithm has been experimented on well known benchmark circuits and shows superior performance compared to various existing algorithms.

• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.202-214
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• 1998

Exploitation of instruction-level parallelism(ILP) is an effective mechanism for improving the performance of modern super-scalar and VLIW processors. Various software techniques can be applied to increase ILP. Among these techniques, predicated execution is the one that increases the degree of ILP by allowing instructions from different basic blocks to be converted to a single basic block by removing branch instructions. In this paper, a global predicate-sensitive scheduling algorithm is proposed to improve the performance for ILP processors that support predicated execution. In order to examine the performance of proposed algorithm, a C compiler and a simulator are developed. By simulating various benchmark programs with the compiler and the simulator, the performance results of this algorithm are measured and the effectiveness of the algorithm is verified. As a result of measure performance with I, 2, 4 issue execution, this study was confirmed average performance by 20% or more.

• Journal of Korean Library and Information Science Society
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• v.40 no.2
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• pp.139-159
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• 2009

This study is to develop knowledge base system for query extension to the user oriented information retrieval. This study has survey the theories of the concept-based information retrieval method and statistic based information retrieval method. In the construction method of knowledge base, the common hypothesis is that the emergence of related term is the frequency of simultaneous emergence of a set of documents. Using the subject index file algorithms and the 'and' operator of boolean logic based on this hypothesis, this study builds the knowledge base. In this research experiment, a subject of knowledge base is education. Using the book of the Introduction to Education, two experimental knowledge base systems is constructed by the different indexing method. One system has constructed by controlled language indexing method, and another system has constructed by natural language indexing method. The performance of two knowledge base system is evaluated.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.4
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• pp.621-628
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• 2017

The efficiency of implementation of the arithmetic operations in finite fields depends on the choice representation of elements of the field. It seems that from this point of view normal bases are the most appropriate, since raising to the power 2 in $GF(2^n)$ of characteristic 2 is reduced in these bases to a cyclic shift of the coordinates. We, in this paper, introduce our algorithm to transform fastly the conventional bases to normal bases and present the result of H/W implementation using the algorithm. We also propose our algorithm to calculate the multiplication and inverse of elements with respect to normal bases in $GF(2^n)$ and present the programs and the results of H/W implementations using the algorithm.

• The Journal of Korean Association of Computer Education
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• v.20 no.4
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• pp.77-84
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• 2017

This paper proposes a tool that can be used as a logical expression simplification tool that can be used for deepening learning of logic circuits and further utilized as a design automation tool for optimizing semiconductor parts. The simplification method of logical expressions proposed in this paper is to find common subexpressions existing in various logical expressions and reduce the repetitive use. Finally, the goal is to minimize the number of literals used in all logical expressions. These previous studies failed to produce a common subexpression embedded in the logical expressions because they only use division principle. The proposed method uses cubes with a Hamming distance of 3 to find the common subexpression embedded between logical expressions. Experiments using benchmark circuits show that the proposed method reduces the number of literals by as much as 47% when comparing simplifications with other methods.

• Journal of the Korea Society of Computer and Information
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• v.20 no.4
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• pp.95-102
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• 2015

This paper proposes a simple algorithm for circuit minimization. There are currently two effective heuristics for circuit minimization, namely manual Karnaugh maps and computable Quine-McCluskey algorithm. The latter, however, has a major defect: the runtime and memory required grow $3^n/n$ times for every increase in the number of variables n. The proposed algorithm, however, extracts the prime implicants (PI) that cover minterms of a given Boolean function by deriving an implicants table based on frequency. From a set of the extracted prime implicants, the algorithm then eliminates redundant PIs again based on frequency. The proposed algorithm is therefore capable of minimizing circuits polynomial time when faced with an increase in n. When applied to various 3-variable and 4-variable cases, it has proved to swiftly and accurately obtain the optimal solutions.

• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2204-2212
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• 1999

In this paper, we present techniques which perform incremental timing analysis using Timed Boolean Algebra that solves the false path problem and extracts the timing information in combinational circuits. Our algorithm sets histories of internal inputs that are substituted for internal output and extracts maximal delays through checking sensitizability of primary outputs. Once finding the sum of primitive delay terms, then it applies modified delay with referencing histories of primary output and it can extract maximal delays of primary outputs fast and efficiently. When the structure of circuit is changed, there is no need to compute the whole circuit again. We can process partial timing analysis of computing on the gates that are need to compute again. These incremental timing analysis methods are considered both delay changes and structure of circuit, and can reduce the costs of a trial error in the circuit design.

• Journal of the Korea Society of Computer and Information
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• v.10 no.4 s.36
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• pp.123-132
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• 2005

A version control system is used in a rapidly changed environment or a program which developed in a complicated environment. And configuration thread information supporting and it's processing method has an important part in version control. Configuration thread tool such as a system model of DSEE, a view of ClearCase, a label of SourceSafe, and the package of CCC/Harvest have applied to formalized configuration rule by user and obtained a desired configuration information of the version. But it is a problem of configuration thread in supporting information that we. in this method. can't know a exactly well-defined configuration rule information and a predefined information. And these information have a demerit that can't supported the close connection along with undefined version and a meta-information. In this paper. we have modeling a system for these problems to solve and a efficiently configuration thread supported. We also proposed a mixed retrieval model included a boolean retrieval model and a vector retrieval model for support efficiently configuration thread information. We applied and designed the libraries using extended facet method.

• Journal of the Korea Society of Computer and Information
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• v.10 no.3 s.35
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• pp.11-18
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• 2005

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint. This algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by $62.2\%$ than those of DDMAP. And reduced the number of CLBs by $17.6\%$ than those of TEMPLA.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.10
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• pp.1185-1193
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• 1999

최적 스택 필터는 시그널 또는 영상의 임의의 특성 정보를 보존하고자 하는 요구조건에 의해 강제된 구조적 제약 하에서 최대의 잡음제거 효과를 얻을 수 있다. 그리고 임계치 분할 특성과 양의 부울 함수에 기반한 이진 영역에서의 처리 특성은 이 필터가 높은 병렬성을 갖고 있음을 보여준다. 본 논문에서는 두 개의 병렬 계산 모델 MCC(Mesh-Connected Computer)와 CCC(Cube-Connected Computer)에서 최적 스택 필터를 위한 1차원 병렬 알고리즘을 개발한다. 최적 스택 필터의 실행 시간은 주로 이진 median 연산에 의해 결정되고 본 논문에서 제안된 알고리즘은 선형 분리성에 의해 이 연산을 구현한다. 이를 바탕으로, M 레벨의 1-D 시그널의 길이가 L이고 윈도우 폭이 N이라고 가정할 때, 제안된 알고리즘은 {{{{root M times root M`` MCC에서 O(L sqrt{M}`) 시간에 그리고 M 개의 PE를 갖는 CCC에서 O(L log M)시간에 수행될 수 있다. 또한 잡음을 더욱 효과적으로 제거하기 위해 윈도우 폭 N을 증가시킬 때, 제안된 병렬 알고리즘의 계산 시간은 일정하게 유지됨을 보인다.Abstract An optimal stack filter achieves the maximum noise attenuation under the structural constraints imposed by the requirement of preserving certain signal or image features. And the filter provides a high parallelism due to the principles of threshold decomposition and binary processing based on positive Boolean functions(PBFs). In this paper, we develop an one-dimensional parallel algorithm for the optimal stack filter on two parallel computation models, MCC(Mesh-Connected Computer) and CCC(Cube-Connected Computer). The running time of the optimal stack filter depends mainly on the binary median operation and our algorithm realizes this operation by the linear separability. Based on this scheme, our parallel algorithm can be performed in {{{{O(L sqrt{M}`) MCC and inO(L log M) time on CCC with M PEs, when the length of M``-valued 1-D signal is L`` and window width is N`` Also, we show that the computation time of our parallel algorithm keeps constant when the window width N increases in order to achieve the best noise attenuation.