• Journal of Navigation and Port Research
• /
• v.39 no.4
• /
• pp.293-297
• /
• 2015

Underwater acoustic communications has been limited use for military purposes in the past. However, the fields of underwater applications expend to detection, submarine and communication in recent. The excessive multipath encountered in underwater acoustic communication channel is creating inter symbol interference, which is limiting factor to achieve a high data rate and bit error rate performance. To improve the performance of a received signal in underwater communication, many researchers have been studied for channel coding scheme with excellent performance at low SNR. In this paper, we applied BCJR decoder based ( 2,1,7 ) convolution codes and to compensate for the distorted data induced by the multipath, we applying the turbo equalization method. Through the underwater experiment on the Gyeungcheun lake located in Mungyeng city, we confirmed that turbo equalization structure of BCJR has better performance than hard decision and soft decision of Viterbi decoding. We also confirmed that the error rate of decoder input is less than error rate of $10^{-1}$, all the data is decoded. We achieved sucess rate of 83% through the experiment.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.47 no.6
• /
• pp.64-72
• /
• 2010

In general, due to the interactions among subsystems, it is difficult to design an decentralized controller for nonlinear interconnected systems. In this study, the model of nonlinear interconnected systems is studied via decentralized fuzzy control method with time delay and polytopic uncertainty. First, the nonlinear interconnected system is represented by an equivalent Takagi-Sugeno type fuzzy model. And the represented model can be rewritten as Parameterized Linear Matrix Inequalities(PLMIs), that is, LMIs whose coefficients are functions of a parameter confined to a compact set. We show that the resulting fuzzy controller guarantees the asymptotic stability and disturbance attenuation of the closed-loop system in spite of controller gain variations within a resulted polytopic region by example and simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.11
• /
• pp.6-12
• /
• 2010

A sigma-delta modulator based class-D audio amplifier is presented. Parallel digital input is serialized to two-bit output by a fourth-order digital sigma-delta noise shaper. The output of the digital sigma-delta noise shaper is applied to a fourth-order analog sigma-delta modulator whose three-level output drives power switches. The pulse density modulated (PDM) output of the power switches is low-pass filtered by an LC-filter. The PDM output of the power switches is fed back to the input of the analog sigma-delta modulator. The first integrator of the analog sigma-delta modulator is a hybrid of continuous-time (CT) and switched-capacitor (SC) integrator. While the sampled input is applied to SC path, the continuous-time feedback signal is applied to CT path to suppress the noise of the PDM output. The class-D audio amplifier is fabricated in a standard $0.13-{\mu}m$ CMOS process and operates for the signal bandwidth from 100-Hz to 20-kHz. With 4-${\Omega}$ load, the maximum output power is 18.3-mW. The total harmonic distortion plus noise and dynamic range are 0.035-% and 80-dB, respectively. The modulator consumes 457-uW from 1.2-V power supply.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.9C
• /
• pp.871-878
• /
• 2002

The cartesian loop chip which is one of key devices in narrow-band Walky-Talky transmitter using RZ-SSB modulation method was designed and implemented with 0.35 ㎛ CMOS technology. The reduced size and low cost of transmitter were available by the use of direct-conversion and cartesian loop chip, which improved the power efficiency and linearity of transmitter. In addition, low power operation was possible through CMOS technology. The performance test results of transmitter showed -23㏈c improvement of IMD and -30㏈c below suppression of SSB characteristic in the operation of cartesian loop chip (closed-loop). At that time, the transmitting power was about 37㏈m (5W). The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.10
• /
• pp.1982-1990
• /
• 1994

We implemented a PLDRO(Phase Locked Dielectric Resonator Oscillator) using the concept of the feedback property of PLL(Phase Locked Loop) for Ku-band(10.95-11.70 GHz). The conventional approaches to a PLDRO design use varactor diode tuning method.. But in theis paper, the PLDRO has the advantage of the frequency sensitivity to changes in the supple voltage of the oscillating device without the frequency-variable part by varactor diode voltage-control. and uses a SPD(Sampling Phase Detector) for phase-comparision. The PLDRO is composed of the DRO phase-locked to the reference signal of UHF band by using a SPD for high frequency stability and can be available for European FSS(Fixed Satellite Service) at 10.00GHz. The PLDRO generates the output power of 8.67 dBm at 10.00 GHz and has a phase noise of -81 dBc/Hz at 10 kHz offset from carrier. The hamonic and spurious characteristics have -42.33 dBc and -65dBc respectively. This PLDRO has much better frequency stability, lower phase noise, and more economical effect for a satellite system than conventional DRO.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.4 no.4
• /
• pp.349-356
• /
• 1999

This paper presents an instantaneous voltage control scheme of au킹liary power supply system for the electric railway v vehicles, The resonance problem of the LC filter and the existing steady state error are more serious as the use of l instantaneous voltage control techniques for the fast transient response at the nonlinear load, A filter capacitor current f feedback loop is considered to increase the damping ratio of the voltage transfer function for the suppression of the resonance problem of the LC inverter output filter. To eliminate the steady state en‘or existing in case of the AC l instantaneous voltage control. the high gain transfer function is added to the conventional PI controller. The theoretical a analysis is well described with the simulation results. The validity of the proposed schemes is well verified through the s simulation and expelimental results for the 5 kVA prototype.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.10
• /
• pp.3917-3922
• /
• 2010

In this paper, 3 stage amplifier MMIC was designed and fabricated with U-band optimized epitaxal pHEMT that produced by large signal characterization and modeling for 60 GHz band. The pHEMT used in this paper, the gate $0.12\;{\mu}m$ length and total gate width of $100\;{\mu}m$, $200\;{\mu}m$ has been modeled using the large signal designed with negative feedback and MCLF instead of MIM capacitor for improving stability. Fabricated MMIC $2.5{\times}1.5mm^2$ size, current about 40 mA, operating frequency 59.5~60.5 GHz, gain 19.9~18.6 dB, input matching characteristics -14.6~-14.7 dB, output matching characteristics -11.9~-16.3 dB and output -5 dBm characteristics were obtained.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.37 no.6
• /
• pp.35-41
• /
• 2000

This paper describes a merged-capacitor switching (MCS) technique to improve the signal Processing speed and resolution of CMOS analog-to-digital converters (ADCs). The proposed MCS technique improves a sampling rate by reducing the number of capacitors used in conventional pipelined ADCs. The ADC capacitor mismatch can be minimized without additional power consumption, die area, and the loss of sampling rate, when the size of each unit capacitor is increased as much as the number of capacitors reduced by the MCS technique. It is verified that the ADC resolution based on the proposed MCS technique is extended further by employing a conventional commutated feedback-capacitor switching (CFCS) technique.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.39 no.3
• /
• pp.183-190
• /
• 2002

This paper describes the synthesis of robust and non-fragile H$\infty$ state feedback controllers for linear varying systems with affine parameter uncertainties, and static state feedback controller with structured uncertainty. The sufficient condition of controller existence, the design method of robust and non-fragile H$\infty$ static state feedback controller, and the set of controllers which satisfies non-fragility are presented. The obtained condition can be rewritten as parameterized Linear Matrix Inequalities(PLMls), that is, LMIs whose coefficients are functions of a parameter confined to a compact set. However, in contrast to LMIs, PLMIs feasibility problems involve infinitely many LMIs hence are inherently difficult to solve numerically. Therefore PLMls are transformed into standard LMI problems using relaxation techniques relying on separated convexity concepts. We show that the resulting controller guarantees the asymptotic stability and disturbance attenuation of the closed loop system in spite of controller gain variations within a degree.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.8
• /
• pp.54-61
• /
• 2001

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage ($V_OL$) to be equal to the reference voltage ($V_{OL.ref}$) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1Gb/s. The worst-case variations of $V_{OL.ref}$ and $V_OL$ of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of $20^{\circ}C$ to $90^{\circ}C$ and a supply voltage range of 2.25V to 2.75V, while the worst-case variation of $V_OL$ of the conventional output driver was measured to be 24% at the same temperature and supply voltage ranges.