• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.2
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• pp.1-13
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• 1981

Simple models for analyzing noise factors have been derived for four fundamental types of feedback amplifiers. These models have been obtained by changing equivalent noise sources of feedback networks into equivalent input noise sources of basic amplifiers. They are used to analyse noise factors for these amplifiers. Noise tractors measured for the four types of feedback amplifiers agree with theoretical results.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.4
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• pp.167-172
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• 2023

A low-noise phase-locked loop(PLL) with three negative feedback loops has been proposed. It is not easy to improve noise characteristics with a conventional PLL. The added negative feedback loops reduce the input voltage magnitude of voltage controlled oscillator which determines the jitter characteristics, enabling the improvement of noise characteristics. Simulation results show that the jitter characteristics are improved as a negative feedback loop is added. In the case of power consumption, it slightly rises by about 10%, but jitter characteristics are improved by about two times. The proposed PLL was simulated with Hspice using a 1.8V 180nm CMOS process.

• The Journal of the Acoustical Society of Korea
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• v.24 no.5
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• pp.238-247
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• 2005

In this Paper. we Presents subband design techniques of a compensating filter and adaptive feedback canceller for the digital hearing aid. The sensorineural hearing loss has a hearing threshold that shows a nonlinear characteristic in frequency domain. and its compensation suffers from an echo that produced by an undesired time varying feedback path. Therefore. the digital hearing aid requires the compensator that can adjust gains nonlinearly in frequency bands and eliminate the echo rapidly In the Proposed digital hearing aid. the compensating filter is designed by the adaptive system identification method in subband structure, and the adaptive feedback canceller is designed by the subband affine projection algorithm. The designed compensation filter can control the nonlinear gain in each subband respectively, therefore precise compensation is possible. And the feedback canceller using the subband adaptive filter achieves fast convergence rate. The Performances of the Proposed method are verified by computer simulations as comparing with the behaviors of the previous trials.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1996.06a
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• pp.23-26
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• 1996

본 논문에서는 선형궤환 등화방식과 결정궤환 복조방식을 결합하여 차동 PSK 신호검출에 필요한 등화기 구조를 제안한다. 이 등화기의 출력을 등화기의 궤환부로 입력하기 앞서, 결정궤환 복조방식에 근거하여 적절히 변형함으로써 제안된 구조는 마치 결정궤한 등화기처럼 동작한다. 모의 실험 결과는 실제로 제안된 등화기가 기존의 차동검파 방식의 등화기 보다 월등한 성능을 나타내고, 동기검파를 위한 결정궤환 등화기에 근접한 성능을 가짐을 보여준다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.23-30
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• 2011

This paper presents a Single-Inductor Multiple-Output (SIMO) DC-DC Converter with a negative feedback selection circuit to improve a regulation property at light load and to generate independent multiple outputs. The conventional SIMO DC-DC converter with a fixed negative feedback circuit cannot regulate correctly at light load. The SIMO DC-DC converter with the proposed negative feedback selection circuit has been designed in 0.35um 2-poly 3-metal BCDMOS. This converter is dual output boost converter with the 1.5V input and 2.5V, 3.0V output. The power conversion efficiency varies from 59% at 10mA loads to 85% at 50mA loads.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.811-818
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• 2016

A continuous fine-tuning phase locked loop with an additional negative feedback loop has been proposed. When the phase locked loop is out-of-lock, the phase locked loop has a fast locking characteristic using the continuous band-selection loop. When the phase locked loop is near in-lock, the bandwidth is narrowed with the fine loop. The additional negative feedback loop consists of a voltage controlled oscillator, a frequency voltage converter and its internal loop filter. It serves a negative feedback function to the main phase locked loop, and improves the phase noise characteristics and the stability of the proposed phase locked loop. The additional negative feedback loop makes the continuous fine-tuning loop work stably without any voltage fluctuation in the loop filter. Measurement results of the fabricated phase locked loop in $0.18{\mu}m$ CMOS process show that the phase noise is -109.6dBc/Hz at 2MHz offset from 742.8MHz carrier frequency.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.1
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• pp.1-6
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• 2019

An extremely small size multi-loop phase-locked loop(PLL) keeping phase noise performances has been proposed. It has been designed to have the loop filter made of small single capacitor with multiple Frequency Voltage Converters (FVCs) because the main goal is to make the size of the proposed PLL extremely small. Multiple FVCs which are connected to voltage controlled oscillator(VCO) make multiple negative feedback loops in PLL. Those multiple negative feedback loops enable the PLL with the loop filter made of an extremely small size single capacitor operate stably. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the 1.6ps jitter and $10{\mu}s$ locking time.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.141-143
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• 2018

본 논문은 계통연계형 인버터의 단독운전 방지를 위해 정궤환을 이용한 무효전력 변동기법을 제안하였으며, 구현 및 실험을 통해 단독운전 방지 성능을 검증하였다. PCC 지점에는 양호도($Q_f$) 2.5의 특성을 갖는 3상 RLC 부하가 연결되며, 부하 공진주파수는 60Hz로 설정하였다. 무효전력 변동기법은 일정 크기로 주입되는 무효분과 주파수 편차를 이용한 정궤환으로부터 공급되는 무효분으로 구성된다. 계통연계 운전 시에는 일정한 무효전력 성분만이 공급되며 역률은 0.9975이다. 단독운전 발생 시, 일정 무효전력 때문에 변화된 PCC 주파수와 계통 정격주파수 간의 편차는 정궤환 성분을 활성화하고, 증가된 무효전력에 의한 PCC 주파수 변화를 검출하여 단독운전을 판단한다. 1.7kW 3레벨 T-타입 인버터를 통해 단독운전 방지 성능을 실험하였으며, 검출시간은 각각 53ms, 150ms로써 우수한 성능을 검증하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.197-199
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• 2017

This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF's voltage is inputted to a comparator through small and large RC time constant circuits. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.3
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• pp.9-16
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• 2004

This paper provides an observer-based Η$\infty$ output feedback controller design method for descriptor systems with time-varying delay by just one LMI(linear matrix inequality) condition. The sufficient condition for the existence of controller and the controller design method are presented by perfect LMI approach which can be solved efficiently by convex optimization. The design procedure involves solving an LMI. Since the obtained condition can be expressed as an LMI form all variables including feedback gain and observer gain can be calculated simultaneously by Schur complement changes of variables, and singular value decomposition. Moreover, The proposed controller design algorithm can be extended to the observer-based robust Η$\infty$ output feedback controller design method for descriptor systems with parameter uncertainty and time delay. An example is given to illustrate the results.