• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.12
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• pp.2286-2292
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• 2008

In this paper, we design a RS(23,17) decoder for MB-OFDM(Multiband-Orthogonal Frequency Division Multiplexing) system, in which Modified Euclidean(ME) algorithm is adopted for key equation solver block. The proposed decoder has been optimized for MB-OFDM system so that it has less latency and hardware complexity. Additionally, we have implemented the proposed decoder using Verilog HDL and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 20,710.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.1
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• pp.61-66
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• 2001

In this paper, we design high speed Viterbi decoding algorithm which is aimed for Wireless LAN. Wireless LAN transmits data at rate 6∼54 Mbps. This high speed is not easy to implement Viterbi decoder with single ACS. So parallel ACS butterfly structure is to be used and several time-dependent problem is to be solved. We simulate Viterbi algorithm using new branch metric calculating method to save time, and consider trace back algorithm which is adaptable to high speed Viterbi decoder. With simulated, we determine the structure of Viterbi decoder. This architecture is available to high speed and low power Viterbi decoder.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.50-57
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• 2013

This paper provides a design of high-throughput parallel turbo decoder that is able to decode several packets of various length simultaneously. For high-speed communications, designing of Turbo decoder as parallel structures reduces the long decoding time caused by iterative turbo decode way. Also, by employing the double buffer structure for input and output packets improves the decoder throughput by enabling continuous decoding. Because parallel turbo decoder is designed to be able to decode the packet of the longest length, there exist idle PE's(Processing Element) in the case of decoding packets of short length. The main idea of this paper is to increase the utilization of PE's in parallel Turbo decoder and to improve the decoder throughput by using the idle PE's immediately for the subsequent packets decoding. For this, the control is necessary to enable the concurrent decoding of several short packets and we propose the method of this control. Applying the proposed method, we implemented Turbo Decoder with 32 PE's that can decode packets of 6144 bits maximum. Compared to the conventional Turbo decoder, although the area was increased about 16%, the decoder throughput was improved 28 times for short packets.

• The Journal of the Korea Contents Association
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• v.9 no.2
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• pp.27-35
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• 2009

In this paper, we present result of embedded system based H.264/SVC decoder circuit design and system implementation. To deal with the standardized H.264/SVC functionalities, the presented SVC decoder system is consist of hardware engine design and software with ARM core processor. In order to improve the feasibility and applicability, and reduce the decoder complexity, the implemented system is constructed with only the consideration of IPPP structure scalability without using the full B-picture architecture. Finally, we will show the decoding image result using the designed H.264/SVC decoder system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1238-1244
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• 1999

In this paper, a new design of a triple-erroe-correcting (TEC) Reed-Solomon decoder is presented based on direct decoding method which is more efficient for the case of relatively small error correction capability. The proposed decoder requires only 9 GF(2m) multipliers in obtaining the error-locator polynomial and the error-evaluator polynomial, whereas other decoders needs 24 multipliers. Thus, the attractive feature of this decoder is its remarkable simplicity from the point of view of implementation. Futhermore, the proposed TEC Reed-Solomon decoder has very simple control circuit and short decoding delay. Therefore this decoder can be implemented by simple hardware and also save buffer memory which stores received sequence.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.59-66
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• 1998

In this paper, the high-speed decoder for RS(Reed-Solomon) code, one of the most popular error correcting code, is implemented using VHDL. This RS decoder is designed in transform domain instead of most time domain. Because of the simplicity in structure, transform decoder can be easily realized VLSI chip. Additionally the pipeline architecture, which is similar to a systolic array is applied for all design. Therefore, This transform RS decoder is suitable for high-rate data transfer. After synthesis with FPGA technology, the decoding rate is more 43 Mbytes/s and the area is 1853 LCs(Logic Cells). To compare with other product with pipeline architecture, this result is admirable. Error correcting ability and pipeline performance is certified by computer simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.5B
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• pp.582-591
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• 2001

터보 부호는 반복적인 복호 알고리즘을 사용함으로써 가산성 백색 가우시안 잡음(AWGN) 채널 환경에서 Shannon 한계에 가까운 성능을 보이는 오류정정 방식으로 제안되었으나, 반복 연산량에 따른 복호 지연과 인터리버에 따른 지연에 의해 실시간 처리의 어려움이라는 문제점을 안고 있다. 본 논문에서는 터보 부호의 성능을 저하시키지 않는 범위에서 적절한 초기 임계값 설정에 따라 불필요한 반복 복호 횟수를 줄일 수 있는 터보 복호기 구조를 제안한다. 적절한 초기 임계값 설정은 LLR(Log-Likelihood Ratio)값의 평균값과 분산, 복호기의 출력에 대한 BER에 근거하여 여러 번의 모의 실험을 통해서 최적의 값으로 결정된다. 제안한 방식은 초기 임계값을 적절히 선택하면 손실이 없는 범위 내에서 반복횟수를 감소시킴으로써 기존의 정해진 반복횟수로 인한 큰 복호 지연을 미연에 방지하고, 이에 따른 계산량 감소는 저전력의 효과도 가져온다. 성능 평가를 위해 BER = $10^{-6}$이내이고, 전송속도가 32kbps 이상인 IMT2000의 고속 데이터 전송 환경에서 모의 실험을 하였다. 실험 결과로 기존의 정해진 반복횟수를 갖는 터보 복호기에 비해 SNR 변동(0~3dB)에서 평균적으로 55~90% 정도의 감소된 반복횟수를 검증하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.8C
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• pp.522-528
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• 2011

The iterative detection and decoding (IDD) has been shown to dramatically improve the bit error rate (BER) performance of the multiple-input multiple-output (MIMO) communication systems. However, these techniques require a high computational complexity since it is required to compute the soft decisions for each bit. In this paper, we show IDD comprised of sphere decoder with low-density parity check (LDPC) codes and present the tree search strategy, called a layer symbol search (LSS), to obtain soft decisions with a low computational complexity. In addition, an adaptive early termination is proposed to reduce the computational complexity during an iteration between an inner sphere decoder and an outer LDPC decoder. It is shown that the proposed approach can achieve the performance similar to an existing algorithm with 70% lower computational complexity compared to the conventional algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4A
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• pp.539-545
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• 2000

A 40-Mb/s, 64-state, R= 1/2, 3 bit soft decision Viterbi decoder based on Radix-4 method has been designed and fabricated using a FLEX10K CPLD chip in this paper. In order to implement the high-speed Viterbi decoder, the architectures of adder-compare-select(ACS), branch metric calculation(BMC), trace back(TB) are present. In practical designed by ASIC, the speed is faster than that of CPLD by 6~7 times. Therefore, 40 Mb/s Viterbi decoder architecture can be used for high-speed wireless multimedia communications with 200 Mb/s.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.245-248
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• 2001

본 논문에서는 연집 오류(burst error)에 우수한 정정 능력을 보이는 고속 RS(Reed-Solomon) 복호기를 제안한다. 제안된 RS 복호기는 RS(n, k, t); (37 < n ≤ 255, 21 < k ≤ 239, t = 8)의 사양을 지원하며 수정 유클리드 알고리즘(modified Euclid´s algorithm)을 이용한 시스톨릭 어레이(systolic array) 방식의 병렬처리 구조로 설계되었다. 고속 RS 복호기의 효율적인 VSLI 설계를 위하여 새로운 방식의 수정 유클리드 알고리즘 연간 회로를 제안한다. 제안된 수정 유클리드 알고리즘 회로는 2t + 1의 연산 지연 시간을 갖으며 기존 구조의 연산 지연 시간인 3t + 37에 비하여 t = 8 인 경우 약 72%의 연산 지연이 감소하였다. 제안된 구조를 VHDL을 이용하여 설계하였으며 SAMSUNG 0.5㎛(KG80) 라이브러리를 이용하여 논리 합성과 타이밍 검증을 수행하였다. 합성된 RS 복호기의 총 게이트 수는 약 77,000 개이며 최대 80MHz의 동작 속도를 나타내었다.