• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.307-310
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• 2001

A parameterized complex-number multiplier (PCMUL) core IP (Intellectual Property), which can be used as an essential arithmetic unit in baseband signal processing of digital communication systems, is described. The bit-width of the multiplier is parameterized in the range of 8-b~24-b and is user-selectable in 2-b step. The PCMUL_GEN, a core generator with GUI, generates VHDL code of a CMUL core for a specified bit-width. The IP is based on redundant binary (RB) arithmetic and a new radix4 Booth encoding/decoding scheme proposed in this paper. It results in a simplified internal structure, as well as high-speed, low-power, and area-efficient implementation. The designed IP was verified using Xilinx FPGA board.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.7
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• pp.47-53
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• 2004

In this paper we introduce a complex escalator (ESC) structure-Equalizer and investigate its performance in complex channels in QPSK undulation systems. The proposed complex equalizer has the complete orthogonalization property and is independent of eigenvalue spread ratio (ESR) of channel. The proposed complex ESC equalizer shows as 7 times faster convergence speed as that of the conventional complex TDL equalizer algorithms in a complex channel model for QPSK systems.

• School Mathematics
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• v.9 no.2
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• pp.291-312
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• 2007

As a result of observing the 10-th grade text books on mathematics now in use which show the way of introducing complex numbers for the first time, it is easy to see all the text books on mathematics use a quadratic equation $x^2+1=0$ for a new number i. However, Since using the new number i is artificial, this make students get confused in understanding the way of introducing complex numbers. And students who have problems with the quadratic equation can also have difficulty in understanding complex numbers. On the other hand, by using a coordinate plane with ordered pairs and arrows, students can understand complex numbers better because the number system can be extended systematically through intuitive methods. The problem is that how to bring and use ordered pairs and arrows to introduce complex numbers in highschool mathematics. To solve this problem, in this study, We developed a systematic and visible learning contents which make it possible to study the process of the step-by-step extension of number system that will be applied through elementary and middle school curriculum and all the way up to the introduction of complex numbers. After having applied the developed learning contents to the teaching and learning procedure, we can know that the developed learning contents are more efficient than the contents used in the text books on mathematics now in use.

• The Journal of the Acoustical Society of Korea
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• v.10 no.5
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• pp.60-68
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• 1991

압전 복합체 PVDF 의 복소수 탄성, 유전, 압전 상수를 측정하였다. 사용된 방법은 각각 초음파 투과법, 임피던스 분석법, 탄성 표면과 측정을 통한 수치해석을 이용하였고, 측정 치중 일부는 이미 보 고된 값들과 비교해보았다. 측정치의 신뢰성 증명을 위해 동일 기법을 압전 세라믹 PZT-5H에 적용해 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.5 s.311
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• pp.52-61
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• 2006

Orthogonal wavelet tansform which is generally used in image and signal processing applications has limited performance because of lack of shift invariance and low directional selectivity. To overcome these demerits complex wavelet transform has been proposed. In this paper, we present an efficient image denoising method using dual-tree complex wavelet transform and Bernoulli-Gauss prior model. In estimating hyper-parameters for Bernoulli-Gaussian model, we present two simple and non-iterative methods. We use hypothesis-testing technique in order to estimate the mixing parameter, Bernoulli random variable. Based on the estimated mixing parameter, variance for clean signal is obtained by using maximum generalized marginal likelihood (MGML) estimator. We simulate our denoising method using dual-tree complex wavelet and compare our algorithm to well blown denoising schemes. Experimental results show that the proposed method can generate good denoising results for high frequency image with low computational cost.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.11-20
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• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• Korean Journal of Optics and Photonics
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• v.20 no.6
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• pp.328-333
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• 2009

We proposed a three-dimensional holographic display technique without twin image noise by converting a complex hologram to an off-axis hologram. To implement the proposed technique we record the complex hologram of a three dimensional object that is composed of two slides located with different depth locations. We added spatial carrier to the complex hologram and after that, extract the real part of the spatial-carrier-added hologram. This converts the complex hologram to an off-axis hologram. We also reconstruct the off-axis hologram using a spatial light modulator for three dimensional display.

• Journal of the Korea Institute of Military Science and Technology
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• v.24 no.4
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• pp.392-400
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• 2021

Unlike optical equipment, SAR(Synthetic Aperture Radar) has the advantage of obtaining images in all weather, and object detection in SAR images is an important issue. Generally, deep learning-based object detection was mainly performed in real-valued network using only amplitude of SAR image. Since the SAR image is complex data consist of amplitude and phase data, a complex-valued network is required. In this paper, a complex-valued ResNet network is proposed. SAR image object detection was performed by combining the ROI transformer detector specialized for aerial image detection and the proposed complex-valued ResNet. It was confirmed that higher accuracy was obtained in complex-valued network than in existing real-valued network.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2015-2024
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• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.192-193
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• 2011

자기유도방식 무선전력전달용 DQ 인버터의 정적 동작 특성 및 동적 응답 특성을 해석하는데 복소 라플라스 변환을 페이저 변환된 회로에 적용하는 방법을 사용하였다. 최근에 발표된 복소 라플라스-페이저 변환이론이 교류 컨버터의 동적특성을 해석하는데 있어 실용적으로 아주 유용하다는 것이 연구를 통해서 확인되었다. 기존의 라플라스 변환을 복소수 영역으로 확대한 복소 라플라스 변환을 페이저 변환된 회로에 적용하면 전달함수를 구할 수 있어, 시스템의 안정도 분석과 제어기 설계가 가능해진다. 본 논문에서는 이론식을 유도하고 시뮬레이션을 통해 검증하였다.