• Electric Engineers Magazine
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• v.224 no.4
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• pp.15-18
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• 2001

산업체 전력계통에서 전력설비의 이용 효율과 전력 공급의 신뢰성을 높이기 위해 여러 대의 변압기들을 병렬로 운전하는 것이 일반적으로 바람직하다. 그러나 병렬운전 대상인 변압기의 전기적 특성이 다른 경우 자기용량 대 부하 분담률이 달라 변압기 과부하 및 무효전력의 과도한 순환조류가 우려되어 병렬운전을 꺼리는 경향이 있다.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.13 no.7
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• pp.95-114
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• 1995

• The Transactions of the Korea Information Processing Society
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• v.6 no.2
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• pp.485-496
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• 1999

Comparing with sequential programming, parallel programming has additional complexity due to the consideration of parallelism, communication and synchronization of processes. A synergism between users and compliers should be established, each assisting the other to produce high quality parallel programs. On the above underlying philosophy, we developed a parallel Object-Oriented specification language, POOSL, as preliminary works. However, it is still likely to hard for users to write parallel program because users have to consider grammar of POOSL and to write text-based parallel program. It would be more desirable to provide users wit visual environment for effective parallel programming. Therefore, we propose a visual programming environment. VEPO(Visual environment for Parallel Object-Oriented Programming), based on POOSL in order that users can develop parallel programs more easily and conveniently. It aims at supporting a programming environment in which users can represent their programs more naturally and visually I parallel manner with object-oriented concept and essential steps during parallel program development such as program specification, compilation, execution and animation of execution are integrated. VEPO has useful features for parallel processing. Especially, complicated parallel codes for synchronization and communication of processes are automatically generated in the translation phase, so users can be relieved of writing error-prone parallel codes. The system is targeted to the transputer-based parallel system, MC-3. The graphic user interface of VEPO was implemented using Visual C++. Visual programs descirbed on VEPO are translated into Inmos C and executed on MC-3.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.6
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• pp.80-87
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• 2016

We propose a parallel mesh smoothing algorithm using graph coloring and OpenMP library for shared memory many core computer architectures. The proposed algorithm partitions a mesh into independent sets and performs a parallel mesh smoothing using OpenMP library. We study the effect of using various graph coloring and color reordering algorithms on the efficiency of performing the proposed parallel mesh smoothing algorithm. We also investigate the influence of using various OpenMP loop scheduling methods on the parallel mesh smoothing efficiency.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.10
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• pp.38-45
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• 2004

In this paper, a parallel visualization algorithm is proposed for efficient visualization of the massive data generated from large-scale parallel finite element analysis through investigating the characteristics of parallel rendering methods. The proposed parallel visualization algorithm is designed to be highly compatible with the characteristics of domain-wise computation in parallel finite element analysis by using the sort-last-sparse approach. In the proposed algorithm, the binary tree communication pattern is utilized to reduce the network communication time in image composition routine. Several benchmarking tests are carried out by using the developed in-house software, and the performance of the proposed algorithm is investigated.

• Journal of Korea Multimedia Society
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• v.1 no.2
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• pp.154-161
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• 1998

This paper proposes a parallel processor system which processes cultural assets image recognition and retrieval algorithm in real time. A serial algorithm which is developed for the parallel processor system is parallellized. The parallel processor system consists of a control unit, 100 PE(Processing Elements), and 10 Park's multi-access memory systems which has 11 memory modules per each one. The parallel processor system is simulated by CADENCE Verilog-XL which is a package for the hardware simulation. With the same simulated results as that of the serial algorithm, the speed ratio of the parallel algorithm to the serial one is 81. The parallel processor system we proposed is quite effective for cultural assets image processing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.218-224
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• 2001

The objective of Distributed Parallel Computing is to solve the computationally intensive problems, which have several types of parallelism, on a suite of high performance and parallel machines in a manner that best utilizes the capabilities of each machine. In this paper, we propose a computational model including the generalized graph representation method of distributed parallel systems for speedup analysis, and analyze how the super-linear speedup is achieved when scheduling of programs with diverse embedded parallelism modes onto a distributed heterogeneous supercomputing network environment. The proposed representation method can also be applied to simple homogeneous or heterogeneous systems whose components are heterogeneous only in terms of the processor speed. In order to obtain the core speedup, the matching of the parallelism characteristics between tasks and parallel machines should be carefully handled while minimizing the communication overhead.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.11a
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• pp.161-164
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• 2013

본 논문에서는 다양한 멀티미디어 코덱을 고속으로 처리하기 위하여 전용하드웨어가 아닌 병렬 어레이 프로세서 기반의 U-Chip(Universal-Chip) 구조를 제안하고 TSMC 80nm 공정을 사용하여 11,865,090개의 게이트 수를 가지는 칩으로 개발하였다. U-Chip은 역양자화(IQ), 역변환(IT), 움직임 보상(MC) 연산을 위한 $4{\times}16$ 개의 프로세싱 유닛으로 구성된 병렬 어레이 프로세서와 문맥적응적 가변길이디코딩(CAVLC)을 위한 비트스트림 프로세서와 인트라 예측(IP), 디블록킹필터(DF) 연산을 위한 순차 프로세서와 DMAC의 데이터 전송 및 각 프로세서를 제어하여 병렬 파이프라인 스케쥴링을 처리하는 시퀀서 프로세서 등으로 구성된다. 1개의 프로세싱 유닛에 1개의 매크로블록 데이터를 맵핑하여 총 64개의 매크로블록을 병렬처리 하였다. 64개 매크로블록의 대용량 데이터 전송 시간과 각 프로세서들의 연산을 동시에 병렬 파이프라인 함으로서 전체 연산 성능을 높일 수 있는 이점이 있다. 병렬 파이프라인 구조의 H.264 디코더 프로그램을 개발하였고 제작된 U-Chip을 통해 $720{\times}480$ 크기의 베이스라인 프로파일 영상에 대하여 코어 192MHz 동작, DDR 메모리 96MHz 동작에서 30fps의 처리율을 가짐을 확인하였다.

• The Journal of the Korea Contents Association
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• v.16 no.3
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• pp.91-101
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• 2016

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.07a
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• pp.290-293
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• 2012

본 논문에서는 기존 AVC 보다 50% 압축성능 향상을 목표로 표준화가 진행되고 있는 차세대표준인 HEVC 부호화기의 속도를 높이기 위한 방안으로, HEVC 의 기술 중 화면 분할 기술인 타일(Tile)을 기반으로 효율적으로 부호화기를 병렬화하는 구조를 제안한다. 부호화기에서 복잡도가 높은 율왜곡 기반 모드 결정 과정을 멀티코어 병렬프로그래밍으로 구현하고, 병렬처리에 의한 속도 개선 결과를 제시한다. 타일은 병렬처리를 지원하기 위해 HEVC 가 채택한 구조로, 화면을 여러 개로 분할하여 부/복호화 할 수 있어 병렬처리 단위로 적합하며, 표준화의 기고서를 통해 화면분할로 인한 압축성능 변화량은 여러 차례 보고되고 있다. 본 논문의 결과에 의하면 타일의 수만큼 쓰레드를 생성하여 각 타일 단위로 율왜곡 기반 부호화 모드 결정을 하도록 병렬화 하였을 때 기존 참조 소프트웨어 대비 12 개의 쓰레드 생성 시 6 배의 속도 개선을 보인다. 향후 병렬로 처리할 수 있는 모듈을 확장하면 쓰레드 수 증가에 따른 속도개선 효과가 증대되어 부호화기 실용화를 위한 실시간 부호화기 개발에 한 걸음 다가갈 수 있을 것이라 기대한다.