• Title/Summary/Keyword: 병렬처리 알고리즘

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The hybrid of artificial neural networks and case-based reasoning for intelligent diagnosis system (인공 신경경망과 사례기반추론을 혼합한 지능형 진단 시스템)

  • Lee, Gil-Jae;Kim, Chang-Joo;Ahn, Byung-Ryul;Kim, Moon-Hyun
    • The KIPS Transactions:PartB
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    • v.15B no.1
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    • pp.45-52
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    • 2008
  • As the recent development of the IT services, there is a urgent need of effective diagnosis system to present appropriate solution for the complicated problems of breakdown control, a cause analysis of breakdown and others. So we propose an intelligent diagnosis system that integrates the case-based reasoning and the artificial neural network to improve the system performance and to achieve optimal diagnosis. The case-based reasoning is a reasoning method that resolves the problems presented in current time through the past cases (experience). And it enables to make efficient reasoning by means of less complicated knowledge acquisition process, especially in the domain where it is difficult to extract formal rules. However, reasoning by using the case-based reasoning alone in diagnosis problem domain causes a problem of suggesting multiple causes on a given symptom. Since the suggested multiple causes of given symptom has the same weight, the unnecessary causes are also examined as well. In order to resolve such problems, the back-propagation learning algorithm of the artificial neural network is used to train the pairs of the causes and associated symptoms and find out the cause with the highest weight for occurrence to make more clarified and reliable diagnosis.

The Motion Estimator Implementation with Efficient Structure for Full Search Algorithm of Variable Block Size (다양한 블록 크기의 전역 탐색 알고리즘을 위한 효율적인 구조를 갖는 움직임 추정기 설계)

  • Hwang, Jong-Hee;Choe, Yoon-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.11
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    • pp.66-76
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    • 2009
  • The motion estimation in video encoding system occupies the biggest part. So, we require the motion estimator with efficient structure for real-time operation. And for motion estimator's implementation, it is desired to design hardware module of an exclusive use that perform the encoding process at high speed. This paper proposes motion estimation detection block(MED), 41 SADs(Sum of Absolute Difference) calculation block, minimum SAD calculation and motion vector generation block based on parallel processing. The parallel processing can reduce effectively the amount of the operation. The minimum SAD calculation and MED block uses the pre-computation technique for reducing switching activity of the input signal. It results in high-speed operation. The MED and 41 SADs calculation blocks are composed of adder tree which causes the problem of critical path. So, the structure of adder tree has changed the most commonly used ripple carry adder(RCA) with carry skip adder(CSA). It enables adder tree to operate at high speed. In addition, as we enabled to easily control key variables such as control signal of search range from the outside, the efficiency of hardware structure increased. Simulation and FPGA verification results show that the delay of MED block generating the critical path at the motion estimator is reduced about 19.89% than the conventional strukcture.

Real-time Color Recognition Based on Graphic Hardware Acceleration (그래픽 하드웨어 가속을 이용한 실시간 색상 인식)

  • Kim, Ku-Jin;Yoon, Ji-Young;Choi, Yoo-Joo
    • Journal of KIISE:Computing Practices and Letters
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    • v.14 no.1
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    • pp.1-12
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    • 2008
  • In this paper, we present a real-time algorithm for recognizing the vehicle color from the indoor and outdoor vehicle images based on GPU (Graphics Processing Unit) acceleration. In the preprocessing step, we construct feature victors from the sample vehicle images with different colors. Then, we combine the feature vectors for each color and store them as a reference texture that would be used in the GPU. Given an input vehicle image, the CPU constructs its feature Hector, and then the GPU compares it with the sample feature vectors in the reference texture. The similarities between the input feature vector and the sample feature vectors for each color are measured, and then the result is transferred to the CPU to recognize the vehicle color. The output colors are categorized into seven colors that include three achromatic colors: black, silver, and white and four chromatic colors: red, yellow, blue, and green. We construct feature vectors by using the histograms which consist of hue-saturation pairs and hue-intensity pairs. The weight factor is given to the saturation values. Our algorithm shows 94.67% of successful color recognition rate, by using a large number of sample images captured in various environments, by generating feature vectors that distinguish different colors, and by utilizing an appropriate likelihood function. We also accelerate the speed of color recognition by utilizing the parallel computation functionality in the GPU. In the experiments, we constructed a reference texture from 7,168 sample images, where 1,024 images were used for each color. The average time for generating a feature vector is 0.509ms for the $150{\times}113$ resolution image. After the feature vector is constructed, the execution time for GPU-based color recognition is 2.316ms in average, and this is 5.47 times faster than the case when the algorithm is executed in the CPU. Our experiments were limited to the vehicle images only, but our algorithm can be extended to the input images of the general objects.

QoS-Guaranteed IP Mobility Management For Fast Moving Vehicles Using Multiple Tunnels (멀티 터널링을 이용한 고속 차량에서 QoS 보장 IP 이동성 관리 방법)

  • Chun, Seung-Man;Nah, Jae-Wook;Park, Jong-Tae
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.48 no.11
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    • pp.44-52
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    • 2011
  • In this article, we present a QoS-guaranteed IP mobility management scheme of Internet service for fast moving vehicles with multiple wireless network interfaces. The idea of the proposed mechanism consists of two things. One is that new wireless connections are established to available wireless channels whenever the measured data rate at the vehicle equipped with mobile gateway drops below to the required data rate of the user requirement. The other is that parallel distribution packet tunnels between an access router and the mobile gateway are dynamically constructed using multiple wireless network interfaces in order to guarantee the required data rate during the mobile gateway's movement. By doing these methods, the required data rate of the mobile gateway can be preserved while eliminating the possible delay and packet loss during handover operation, thus resulting in the guaranteed QoS. The architecture of the IETF standard HMIPv6 has been extended to realize the proposed scheme, and detailed algorithms for the extension of HMIPv6 has been designed. Finally, simulation has been done for performance evaluation, and the simulation results show that the proposed mechanism demonstrates guaranteed QoS during the handover with regard to the handover delay, packet loss and throughput.

Rear Vehicle Detection Method in Harsh Environment Using Improved Image Information (개선된 영상 정보를 이용한 가혹한 환경에서의 후방 차량 감지 방법)

  • Jeong, Jin-Seong;Kim, Hyun-Tae;Jang, Young-Min;Cho, Sang-Bok
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.1
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    • pp.96-110
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    • 2017
  • Most of vehicle detection studies using the existing general lens or wide-angle lens have a blind spot in the rear detection situation, the image is vulnerable to noise and a variety of external environments. In this paper, we propose a method that is detection in harsh external environment with noise, blind spots, etc. First, using a fish-eye lens will help minimize blind spots compared to the wide-angle lens. When angle of the lens is growing because nonlinear radial distortion also increase, calibration was used after initializing and optimizing the distortion constant in order to ensure accuracy. In addition, the original image was analyzed along with calibration to remove fog and calibrate brightness and thereby enable detection even when visibility is obstructed due to light and dark adaptations from foggy situations or sudden changes in illumination. Fog removal generally takes a considerably significant amount of time to calculate. Thus in order to reduce the calculation time, remove the fog used the major fog removal algorithm Dark Channel Prior. While Gamma Correction was used to calibrate brightness, a brightness and contrast evaluation was conducted on the image in order to determine the Gamma Value needed for correction. The evaluation used only a part instead of the entirety of the image in order to reduce the time allotted to calculation. When the brightness and contrast values were calculated, those values were used to decided Gamma value and to correct the entire image. The brightness correction and fog removal were processed in parallel, and the images were registered as a single image to minimize the calculation time needed for all the processes. Then the feature extraction method HOG was used to detect the vehicle in the corrected image. As a result, it took 0.064 seconds per frame to detect the vehicle using image correction as proposed herein, which showed a 7.5% improvement in detection rate compared to the existing vehicle detection method.

A Hardware Implementation of the Underlying Field Arithmetic Processor based on Optimized Unit Operation Components for Elliptic Curve Cryptosystems (타원곡선을 암호시스템에 사용되는 최적단위 연산항을 기반으로 한 기저체 연산기의 하드웨어 구현)

  • Jo, Seong-Je;Kwon, Yong-Jin
    • Journal of KIISE:Computing Practices and Letters
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    • v.8 no.1
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    • pp.88-95
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    • 2002
  • In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.