• Journal of the Korea Computer Graphics Society
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• v.24 no.3
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• pp.21-31
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• 2018

We introduces a system that enables fast and effective visualization of natural disaster data such as typhoons, tsunamis, floods, and flooding to help make informed decisions in disaster situations. Data containing disaster information consists of a few hundred megabytes to many tens and hundreds of gigabytes, which can not be handled by a PC. This system was implemented in the form of a client-server based service to generate and output results from high-performance servers. The server in a built-in, high-performance cluster handles client requests and sends the result of visualization to the client. Clients can receive the results in any form of images, videos, or 3D graphic model by specifying a desired time frame, effectively viewing the results with a user-friendly GUI.

• KIPS Transactions on Software and Data Engineering
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• v.3 no.11
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• pp.479-486
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• 2014

MapReduce is a programing model used for parallelly processing a large amount of data. To analyze a large amount data, the data cube is widely used, which is an operator that computes group-bys for all possible combinations of given dimension attributes. When the number of dimension attributes is n, the data cube computes $2^n$ group-bys. In this paper, we propose an efficient method for computing data cubes using MapReduce. The proposed method partitions $2^n$ group-bys into $_nC_{{\lceil}n/2{\rceil}}$ batches, and computes those batches in stages using ${\lceil}n/2{\rceil}$ MapReduce jobs. Compared to the existing methods, the proposed method significantly reduces the amount of intermediate data generated by mappers, so that the cost of sorting and transferring those intermediate data is reduced significantly. Consequently, the total processing time for computing a data cube is reduced. Through experiments, we show the efficiency of the proposed method over the existing methods.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.660-669
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• 2010

In this paper, a multiple antenna system for next generation mobile applications is proposed. The proposed MIMO antenna consists of two parallel folded monopole antennas with the length of 100 mm and spacing of 6 mm and a decoupling network which locates at the top side of a mobile handset. In order to improve the isolation characteristic at the LTE band 13, a decoupling network was added between the two antenna elements placed close to each other. The decoupling network, consisting of two transmission lines, a shunt reactive component and common ground line, is simple and compact. To obtain the wide bandwidth characteristic, an wide folded patch structure generating the strong coupling between feeding and shorting lines through the slit is used at the bottom side of a mobile handset. Also, the performance of a multiple antenna system composed of three antenna elements is analyzed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.3
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• pp.661-669
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• 2000

DS-CDMA downlink distinguishes actual user by orthogonal spreading codes ,but its orthogonality may be lost by the multiple access interference(MAI) caused by the multipath channel. Therefore in this paper, we proposed the single-user receiver, which use linear channel equalizer to eliminate the interference due to multipath channel and to recover orthogonality and then use code-matched filter to detect transmitted data. Unlike existing research, which mainly assumed ideal channel information, we use pilot channel assisted methods that is a kind of transmission of a parallel reference method to estimate the channel coefficients. Especially we use guard symbols which are inserted periodically to estimate channel coefficients exactly without interference from user signal. The results show that we accepted an approximately ideal channel information and achieved excellent performance improvement using proposed receiver compared with the conventional receiver especially user populations are high.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.661-668
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• 2012

A coaxial-cable impedance transformer that can be used in high power and wideband frequency range is an arbitrary impedance transformation ratio by an additional coaxial cable. The coaxial-cable impedance transformer to be 50-${\Omega}$ to 25-${\Omega}$ impedance transformation ratio is easily operated an wideband power divider by connecting two 50-${\Omega}$ lines at 25-${\Omega}$ impedance point. This wideband power divider has a poor output matching characteristic and a poor isolation characteristic between two output ports. In this paper, it proposes a coaxial-cable power divider to be a good output matching and isolation characteristics as it uses the singly terminated filter design theory. The odd-mode operation characteristic of the suggested power divider to use singly terminated low pass filter coefficient due to matching order and ripple value is examined by ADS program. And, it fabricates and measures the operation characteristic of 2-way power divider with 2nd-order and 4th-order matching circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.9
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• pp.2041-2047
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• 2013

In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed dc-split memory structure in order to reduced the delay and high speed decoder is possible. Finally, this paper presented maximum split memory and throughput for various coding rates in DVB-S2 standard.

• The Journal of the Korea Contents Association
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• v.9 no.5
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• pp.13-23
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• 2009

One of the main purpose of multiple-view image processing technology is support realistic 3D image to device user by using multiple viewpoint display devices and compressed data restoration devices. This paper proposes a multiple view image synthesis scheme based on RAM disk which makes possible to browse 3D images generated by applying effective composing method to real time input stereo images. The proposed scheme first converts input images to binary image. We applies edge detection algorithm such as Sobel algorithm and Prewiit algorithm to find edges used to evaluate disparities from images of 4 multi-cameras. In addition, we make use of time interval between hardware trigger and software trigger to solve the synchronization problem which has stated ambiguously in related studies. We use a unique identifier on each snapshot of images for distributed environment. With respect of performance results, the proposed scheme takes 0.67 sec in each binary array. to transfer entire images which contains left and right side with disparity information for high quality 3D image browsing. We conclude that the proposed scheme is suitable for real time 3D applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.814-821
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• 2012

We propose a network processor called an OmniFlow processor capable of wire-speed flow management by a hardware-based flow admission control(FAC) in this paper. Because the OmniFlow processor can set up and release a wire-speed connection for flows, the update period of flows can be set to a short time, and only active flows can be effectively managed by terminating a flow that does not have a packet transmitted within this period. Therefore, the FAC can be used to provide a reliable transmission of UDP as well as TCP applications. This processor is fabricated in 65nm CMOS technology, and total gate count is 25 million. It has 40 Gb/s throughput performance in using the 32 RISC cores when maximum operating frequency is 555MHz.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.1
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• pp.66-75
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• 2002

For the theoretical performance analysis of Viterbi Decoder for wireless LAN with data rate 12Mbps, code rate 1/2 and constraint length 7 defined in IEEE 802.11a, the transfer function is derived using Cramer's rule and the first-event error probability and bit error probability is derived under the AWGN. In the design process, input symbol is quantized into 16 steps for 4 bit soft decision and register exchange method instead of memory method is proposed for trace back, which enables the majority at the final decision stage. In the implementation, the Viterbi decoder based on parallel architecture with pipelined scheme for processing 12Mbps high speed data rate and AWGN generator are implemented using FPGA chips. And then its performance is verified in real time.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.105-112
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• 1998

In this paper, we propose a ESP(Extended Scan Path) architecture for multi-board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan path is either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using the proposed ESP architecture, we observed that the test time is short compared with the single scan path architecture. By comparing the ESP architecture with single scan path responding to independency of scan path, test time and with multi-scan path responding to signal, synchronization, we showed that the architecture has improved results.