• The KIPS Transactions:PartA
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• v.11A no.3
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• pp.181-188
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• 2004

PDF(Parallel/Distributed Processing) is an internet-based parallel/distributed processing system that utilizes resources from hosts on the internet in idle state to perform large scale application through parallel processing, thus decreasing the total execution time. In this paper. do propose an adaptive method to be changed network environment at any time using realtime monitoring of host. It is found from experiments that parallel/distributed processing has better performance than its without monitoring as an adaptive strategy, which copy with task delay factor by overload and fault of network, be applicable to the cockpits of task allocation algorithm in PDP.

• Journal of IKEEE
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• v.25 no.1
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• pp.101-108
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• 2021

This paper proposes a parallel control method of a modular DC/DC converter for electric vehicle (EV) chargers. The EV chargers have been increasing the power capacity using modular converters. There are output current imbalances between the modules, which are caused by the difference of the impedance, delay of the gate driver, and error of the sensors. The conventional strategies for the equal distribution of the output current cause the voltage drop or the high volume and cost of the converters. Therefore, the proposed parallel control strategy effectively balances the output current of modules using a current compensation method. The proposed strategy is verified by simulations. Additional experimental results will be added under various conditions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1902-1918
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• 1993

Parallel architecture based on the von Neumann computation model has a limitation as a massively parallel architecture due to its inherent drawback of architectural features. The data-flow model of computation has a high programmability in software perspective and high scalability in hardware perspective. However, the practical programming and experimentaion of date-flow architectures are hardly available due to the absence of practical data-flow, we present a programming environment for performing the data-flow computation on conventional parallel machines in general, loosely compled multiprocessor system in particular. We build an emulator for tagged token data-flow architecture on the iPSC/2 hypercube, a loosely coupled multiprocessor system. The emulator is a shallow layer of software executing on an iPSC/2 system, and thus makes the iPSC/2 system work as a data-flow architecture from the programmer`s viewpoint. We implement various numerical and non-numerical algorithm in a data-flow assembler language, and then compare the performance of the program with those of the versions of conventional C language, Consequently, We verify the effectiveness of this programming environment based on the emulator in experimenting the data-flow computation on a conventional parallel machine.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.22 no.1
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• pp.35-44
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• 2009

This paper describes an application of domain decomposition method for parallel finite element analysis which is required to large scale 3D structural analysis. A parallel finite element method system which adopts a domain decomposition method is developed. Node is generated if its distance from existing node points is similar to the node spacing function at the point. The node spacing function is well controlled by the fuzzy knowledge processing. The Delaunay triangulation method is introduced as a basic tool for element generation. Domain decomposition method using automatic mesh generation system holds great benefits for 3D analyses. Aa parallel numerical algorithm for the finite element analyses, domain decomposition method was combined with an iterative solver, i.e. the conjugate gradient(CG) method where a whole analysis domain is fictitiously divided into a number of subdomains without overlapping. Practical performance of the present system are demonstrated through several examples.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.14 no.3
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• pp.287-298
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• 2001

Analysis of nonlinear behavior of prestressed concrete frame structures on PC is a time-consuming computing job if the problem size increase to a certain degree. Cluster system has emerged as one of promising computing environments due to its good extendibility, portability, and cost-effectiveness, comparing it with high-end work-stations or servers. In this paper, a parallel nonlinear analysis procedure of prestressed concrete frame structure is presented using cluster computing. Cluster system is configured with readily available pentium III class PCs under Win98 or Linux and fast ethernet. Parallel computing algorithms on element-wise processing parts including the calculation of stiffness matrix, element stresses and determination of material states, check of material failure and calculation of unbalanced loads are developed using MPL. Validity of the method is discussed through typical numerical examples. For the case of 4 node system, maximum speedup is 3.15 and 3.74 for Win98 and Linux, respectively. Important issues for the efficient use of cluster computing system based un PCs and ethernet are addressed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.19-28
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• 2000

The parallel inverter is widely utilized because of its fault-tolerance capability, high-current output at constant voltages and system modularity. The conventional paralled inverter usually employes an active and reactive power control or a frequency and voltage droop control. However, these approaches have the disadvantages that the response time of parallel inverter control is slow against load and system parameter variation to calculate active, reactive power, frequency and voltage. This paper describes novel control scheme for equalization of output power between the parallel connected inverters. The proposed scheme has a fast power balance control response, a simplicity of implementation, and inherent peak current limiting capability since it employes a instantaneous current/voltage control with output voltage and current balance and output voltage regulation. A design procedure for the proposed parallel inverter controller is presented. Futhermore, the proposed constrol scheme is verified through the simulation in various cases such as the system parameter variation, the control parameter variation and the nonlinear load condition.

• Journal of the Korea Society for Simulation
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• v.24 no.3
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• pp.37-44
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• 2015

A queueing system with 2 parallel workstations is common in the field. Typically, the workstations have different features in terms of the inter arrival times of customers and the service times for the customers. Computer simulation study on the optimal server allocation for parallel heterogeneous queueing systems with fixed number of identical servers is presented in this paper. The queueing system is optimized with respect to minimizing the weighted system time of the customers served by 2 parallel workstations. The system time formula for the M/M/c systems in Kendall's notation is known. Thus, we first compute the optimal allocation for parallel M/M/c systems, comparing the results with those from the computer simulation experiments, and have the same results. The CETI rule is devised through optimizing M/M/c cases, which allocates the servers based on Close or Equal Traffic Intensities between workstations. Traffic intensity is defined as the arrival rate divided by the service rate times the number of servers. The CETI rule is shown to work for M/G/c, G/M/c queueing systems by numerous computer simulation experiments, even if the rule cannot be proven analytically. However, the CETI rule is shown not to work for some of G/G/c systems.

• Journal of Advanced Navigation Technology
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• v.13 no.1
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• pp.62-67
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• 2009

The demand for high performance computer grows to solve large linear systems of equations in such engineering fields - circuit simulation for VLSI design, image processing, structural engineering, aerodynamics, etc. Many various parallel processing systems have been proposed and manufactured to satisfy the demand. The properties of linear system determine what algorithm is proper to solve the problem. Direct methods or iterative methods can be used for solving the problem. In this paper, an intelligent parallel iterative method for solving linear systems of equations with large sparse matrices is proposed and its efficiency is proved through simulation.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2015.07a
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• pp.195-198
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• 2015

최근 TV 서비스의 가입자 및 TV 프로그램 콘텐츠의 급격한 증가에 따라 빅데이터 처리에 적합한 추천 시스템의 필요성이 증가하고 있다. 본 논문은 사용자들의 간접 평가 데이터 기반의 추천 시스템 디자인 시, 누적된 사용자의 과거 이용내역 데이터를 저장하지 않고 새로 생성된 사용자 이용내역 데이터를 학습하는 효율적인 알고리즘이면서, 시간 흐름에 따라 사용자들의 선호도 변화 및 TV 프로그램 스케줄 변화의 추적이 가능한 토픽 모델링 기반의 알고리즘을 제안한다. 빅데이터 처리를 위해서는 분산처리 형태의 알고리즘을 피할 수 없는데, 기존의 연구들 중 토픽 모델링 기반의 추론 알고리즘의 병렬분산처리 과정 중에 핵심이 되는 부분은 많은 데이터를 여러 대의 기계에 나누어 병렬분산 학습하면서 전역변수 데이터를 동기화하는 부분이다. 그런데, 이러한 전역데이터 동기화 기술에 있어, 여러 대의 컴퓨터를 병렬분산처리하기위한 하둡 기반의 시스템 및 서버-클라이언트간의 중재, 고장 감내 시스템 등을 모두 고려한 알고리즘들이 제안되어 왔으나, 네트워크 대역폭 한계로 인해 데이터 증가에 따른 동기화 시간 지연은 피할 수 없는 부분이다. 이에, 본 논문에서는 빅데이터 처리를 위해 사용자들을 클러스터링하고, 클러스터별 제안 알고리즘으로 전역데이터 동기화를 수행한 것과 지역 데이터를 활용하여 추론 연산한 결과, 클러스터별 지역별 TV프로그램 시청 토큰 별 은닉토픽 할당 테이블을 유지할 때 추천 성능이 더욱 향상되어 나오는 결과를 확인하여, 제안된 구조의 추천 시스템 디자인의 효율성과 합리성을 확인할 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.43-53
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• 2010

Wide deployment of high resolution video services leads to active studies on high speed video processing. Especially, prevalent employment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. In this paper, we propose a novel parallel H.264/AVC decoding scheme on a multi-core platform. Parallel H.264/AVC decoding is challenging not only because parallelization may incur significant synchronization overhead but also because software may have complicated dependencies. To overcome such issues, we propose a novel approach called Multi-Threaded Parallelization(MTP). In MTP, to reduce synchronization overhead, a separate thread is allocated to each stage in the pipeline. In addition, an efficient memory reuse technique is used to reduce the memory requirement. To verify the effectiveness of the proposed approach, we parallelized FFmpeg H.264/AVC decoder with the proposed technique using OpenMP, and carried out experiments on an Intel Quad-Core platform. The proposed design performs better than FFmpeg H.264/AVC decoder before the parallelization by 53%. We also reduced the amount of memory usage by 65% and 81% for a high-definition(HD) and a full high-definition(FHD) video, respectively compared with that of popular existing method called 2Dwave.