• Journal of Korea Multimedia Society
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• v.7 no.8
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• pp.1183-1194
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• 2004

Network partitioning problem is to partition a network into multiple blocks such that the size of cutset is minimized while keeping the block sizes balanced. Among these, iterative algorithms are regarded as simple and efficient which are based on cell move of Fiduccia and Mattheyses algorithm, Sanchis algorithm, or Kernighan and Lin algorithm. All these algorithms stipulate balanced block size as a constraint that should be satisfied, which makes a cell movement be inefficient. Park and Park introduced a balancing coefficient R by which the block size balance is considered as a part of partitioning cost, not as a constraint. However, Park and Park's algorithm has a square time complexity with respect to the number of cells. In this paper, we proposed Bucket algorithm that has a linear time complexity with respect to the number of cells, while taking advantage of the balancing coefficient. Reducing time complexity is made possible by a simple observation that balancing cost does not vary so much when a cell moves. Bucket data structure is used to maintain partitioning cost efficiently. Experimental results for MCNC test sets show that cutset size of proposed algorithm is 63.33% 92.38% of that of Sanchis algorithm while our algorithm satisfies predefined balancing constraints and acceptable execution time.

• The KIPS Transactions:PartD
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• v.9D no.5
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• pp.755-768
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• 2002

We investigate the effect of the data skew of join attributes on the performance of a pipelined multi-way hash join method, and propose two new hash join methods with load balancing capabilities. The first proposed method allocates buckets statically by round-robin fashion, and the second one allocates buckets adaptively via a frequency distribution. Using hash-based joins, multiple joins can be pipelined so that the early results from a join, before the whole join is completed, are sent to the next join processing without staying on disks. Unless the pipelining execution of multiple hash joins includes some load balancing mechanisms, the skew effect can severely deteriorate system performance. In this paper, we derive an execution model of the pipeline segment and a cost model, and develop a simulator for the study. As shown by our simulation with a wide range of parameters, join selectivities and sizes of relations deteriorate the system performance as the degree of data skew is larger. But the proposed method using a large number of buckets and a tuning technique can offer substantial robustness against a wide range of skew conditions.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.5
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• pp.294-302
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• 2020

In a genetic algorithm, computer simulations are performed based on the natural evolution process of life, such as selection, crossover, and mutation. The genetic algorithm searches the approximate optimal solution by the parallel arrangement of Schema, which has a short definition length, low order, and high adaptability. This study examined the possibility of improving the efficiency of the optimal solution by considering the characteristics of the building block hypothesis, which are one of the key operating principles of a genetic algorithm. This study evaluated the efficiency of the optimization results according to the gene sequence for the implementation in solving problems. The optimal design problem of the water pipe was selected, and the genetic arrangement order reflected the engineering specificity by dividing into the existing, the network topology-based, and the flowrate-based arrangement. The optimization results with a flowrate-based arrangement were, on average, approximately 2-3% better than the other batches. This means that to increase the efficiency of the actual engineering optimization problem, a methodology that utilizes clear prior knowledge (such as hydraulic properties) to prevent such excellent solution characteristics from disappearing is essential. The proposed method will be considered as a tool to improve the efficiency of large-scale water supply network optimization in the future.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.252-259
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• 2007

With the rapid development of multimedia applications and wireless communication networks, consumer demand for video-over-wireless capability on mobile computing systems is growing rapidly. In this regard, this paper introduces YUV-aware instructions that enhance the performance and efficiency in the processing of color image and video. Traditional multimedia extensions (e.g., MMX, SSE, VIS, and AltiVec) depend solely on generic subword parallelism whereas the proposed YUV-aware instructions support parallel operations on two-packed 16-bit YUV (6-bit Y, 5-bits U, V) values in a 32-bit datapath architecture, providing greater concurrency and efficiency for color image and video processing. Moreover, the ability to reduce data format size reduces system cost. Experiment results on a representative dynamically scheduled embedded superscalar processor show that YUV-aware instructions achieve an average speedup of 3.9x over the baseline superscalar performance. This is in contrast to MMX (a representative Intel#s multimedia extension), which achieves a speedup of only 2.1x over the same baseline superscalar processor. In addition, YUV-aware instructions outperform MMX instructions in energy reduction (75.8% reduction with YUV-aware instructions, but only 54.8% reduction with MMX instructions over the baseline).

• Korean Journal of Cognitive Science
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• v.22 no.1
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• pp.57-78
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• 2011

Paraphrasing is the act of writing a text using other words without altering the meaning. Paraphrases can be used in many fields of natural language processing. In particular, paraphrases can be incorporated in machine translation in order to improve the coverage and the quality of translation. Recently, the approaches on paraphrase extraction utilize bilingual parallel corpora, which consist of aligned sentence pairs. In these approaches, paraphrases are identified, from the word alignment result, by pivot phrases which are the phrases in one language to which two or more phrases are connected in the other language. However, the word alignment is itself a very difficult task, so there can be many alignment errors. Moreover, the alignment errors can lead to the problem of selecting incorrect pivot phrases. In this study, we propose a method in paraphrase extraction that discriminates good pivot phrases from bad pivot phrases. Each pivot phrase is weighted according to its reliability, which is scored by considering the lexical and part-of-speech information. The experimental result shows that the proposed method achieves higher precision and recall of the paraphrase extraction than the baseline. Also, we show that the extracted paraphrases can increase the coverage of the Korean-English machine translation.

• Korean Chemical Engineering Research
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• v.46 no.3
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• pp.585-597
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• 2008

The aim of this study was to find an analytic solution to the problem of determining the optimal capacity (lot-size) of a batch-storage network to meet demand for a finished product in a system undergoing random failures of operating time and/or batch material. The superstructure of the plant considered here consists of a network of serially and/or parallel interlinked batch processes and storage units. The production processes transform a set of feedstock materials into another set of products with constant conversion factors. The final product demand flow is susceptible to short-term random variations in the cycle time and batch size as well as long-term variations in the average trend. Some of the production processes have random variations in product quantity. The spoiled materials are treated through regeneration or waste disposal processes. All other processes have random variations only in the cycle time. The objective function of the optimization is minimizing the total cost, which is composed of setup and inventory holding costs as well as the capital costs of constructing processes and storage units. A novel production and inventory analysis, the PSW (Periodic Square Wave) model, provides a judicious graphical method to find the upper and lower bounds of random flows. The advantage of this model is that it provides a set of simple analytic solutions while also maintaining a realistic description of the random material flows between processes and storage units; as a consequence of these analytic solutions, the computation burden is significantly reduced.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.756-759
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• 2015

As the struggle to get a job becomes increasingly ferocious year after year, the website offering a range of employment information have continued to gain popularity. Those website, however, are not of much help when it comes to an interview to face the interviewer. Furthermore, many people suffer depression due to the heavy stress they are under while making preparations for employment or working for an organization. The current employment website do not have a team of professionals to deal with such issues. In an effort to solve those problems, the present study made arrangements to allow users to put in an enormous amount of employment information based on Google App Engine(GAE) and Google Web Toolkit(GWT) and upload interview videos. In addition, a Q&A board was created to help those who prepare for employment or current workers relieve their stress and provide them with access to a team of counseling professionals.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.25-32
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• 2011

Networks-on-chip (NoC) is emerging as a key technology to overcome severe bus traffics in ever-increasing complexity of the Multiprocessor systems-on-chip (MPSoC); however traditional electrical interconnection based NoC architecture would be faced with technical limits of bandwidth and power consumptions in the near future. In order to cope with these problems, a hybrid optical NoC architecture which use both electrical interconnects and optical interconnects together, has been widely investigated. In the hybrid optical NoCs, wormhole switching and simple deterministic X-Y routing are used for the electrical interconnections which is responsible for the setup of routing path and optical router to transmit optical data through optical interconnects. Optical NoC uses circuit switching method to send payload data by preset paths and routers. However, conventional hybrid optical NoC has a drawback that concurrent transmissions are not allowed. Therefore, performance improvement is limited. In this paper, we propose a new routing algorithm that uses circuit switching and adaptive algorithm for the electrical interconnections to transmit data using multiple paths simultaneously. We also propose an efficient method to prevent livelock problems. Experimental results show up to 60% throughput improvement compared to a hybrid optical NoC and 65% power reduction compared to an electrical NoC.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.188-198
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• 2013

In order to increase its performance, NAND flash memory-based storage is composed of data buses that are shared by a number of flash memories and uses a parallel technique that can carry out multiple flash memory operations simultaneously. Since the storage performance is strongly influenced by the performance of each data bus, it is important to improve the utilization of the bus by ensuring effective scheduling of operations by the storage controller. However, this is difficult because of dynamic changes in buses due to the unique characteristics of each operation with different timing, cost, and usage by each bus. Furthermore, the scheduling technique for increasing bus utilization may cause unanticipated operation delay and wastage of storage resource. In this study, we suggest various dynamic operation scheduling techniques that consider data bus performance and storage resource efficiency. The proposed techniques divide each operation into three different stages and schedule each stage depending on the characteristics of the operation and the dynamic status of the data bus. We applied the suggested techniques to the controller and verified them on the FPGA platform, and found that program operation decreased by 1.9% in comparison to that achieved by a static scheduling technique, and bus utilization and throughput was approximately 4-7% and 4-19% higher, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.41-49
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• 2010

This paper proposes a new high speed SHA-1 architecture using multiple unfolding and pre-computation techniques. We unfolds iterative hash operations to 2 continuos hash stage and reschedules computation timing. Then, the part of critical path is computed at the previous hash operation round and the rest is performed in the present round. These techniques reduce 3 additions to 2 additions on the critical path. It makes the maximum clock frequency of 118 MHz which provides throughput rate of 5.9 Gbps. The proposed architecture shows 26% higher throughput with a 32% smaller hardware size compared to other counterparts. This paper also introduces a analytical model of multiple SHA-1 architecture at the system level that maps a large input data on SHA-1 block in parallel. The model gives us the required number of SHA-1 blocks for a large multimedia data processing that it helps to make decision hardware configuration. The hs fospeed SHA-1 is useful to generate a condensed message and may strengthen the security of mobile communication and internet service.