• Title/Summary/Keyword: 벤치마크 기법

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A Transparent Monitor for Filtering Access Events to Shared Variables in Concurrent Java Programs (병행 Java 프로그램의 공유변수 접근사건 선택을 위한 투명한 감시도구)

  • Kuh, In-Bon;Kim, Young-Joo;Kang, Moon-Hye;Jun, Yong-Kee
    • Annual Conference of KIPS
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    • 2007.11a
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    • pp.648-652
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    • 2007
  • 병행 Java 프로그램의 경합은 프로그램의 비결정성을 초래하므로 반드시 탐지되어야 한다. 이러한 경합을 수행 중에 탐지하기 위해서는 모든 접근사건들을 감시할 수 있어야 한다. 기존의 경합탐지 기법들은 대상 프로그램을 수정하여 감시하므로 모든 감시지점을 인식하는 것은 현실적으로 어렵다. 본 연구에서는 JDI (Java Debug Interface)를 이용하여 모든 접근사건을 감시하여 선택할 수 있는 투명한 감시도구를 제안한다. 그리고 벤치마크 프로그램을 이용한 실험결과를 분석하여 투명성을 보인다.

Shadow stack performance evaluation in RISC-V architecture (RISC-V 아키텍처에서의 쉐도우 스택 성능평가)

  • Ha-Young Kang;Seong-Hwan Park;Dong-Hyun Kwon
    • Annual Conference of KIPS
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    • 2024.05a
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    • pp.354-357
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    • 2024
  • 본 연구에서는 RISC-V 아키텍처를 대상으로 쉐도우 스택을 적용한 벤치마크의 성능을 평가하였다. 이를 통해 RISC-V 아키텍처 상에서 쉐도우 스택이 가지는 성능 오버헤드를 측정하였다. 실험 결과, 평균 2.75%의 성능 오버헤드를 보여주었으며 이는 기준선 대비 무시할 만한 성능 오버헤드가 발생함을 보여주었다. 이러한 결과는 RISC-V 아키텍처에서 쉐도우 스택이 보안 강화에 유용하게 활용될 수 있음을 시사하며, 이를 통해 새로운 보안 메커니즘의 도입에 대한 가능성을 열어두고자 한다. 이 연구는 RISC-V 아키텍처를 기반으로 한 보안 강화 기법의 효과적인 적용에 대한 중요한 기여를 제공할 것으로 기대된다.

Performance Evaluation of the Roll-back Recovery on the Cluster System with SIOS (SIOS 기반의 저장 장치를 사용하는 클러스터 시스템의 결함 회복 성능 평가)

  • Yu, Taek-Geun;Chang, Yun-Seok
    • Annual Conference of KIPS
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    • 2007.05a
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    • pp.773-776
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    • 2007
  • 클러스터 시스템에서 결함이 발생하였을 때, 결함 회복 성능은 매우 중요한 설계 요소가 된다. 단일 입출력 공간(SIOS)을 저장 장치로 사용하는 클러스터 시스템에서, 각 노드들의 결함허용정보를 주기적으로 저장하는 roll-back 결함회복 기법을 사용하는 경우, 결함 회복 성능은 SIOS가 제공하는 입출력 병렬성과 깊은 관계가 있다. 본 연구에서는 클러스터 시스템의 SIOS 구성에 참여하는 노드 수에 따른 결함 회복 성능을 HPL 벤치마크를 통하여 여러 환경에서 평가하고, 그 결과를 분석하였다. 성능 평가 수행 결과, 클러스터 시스템은 SIOS 구성에 참여하는 노드의 수가 증가할수록 우수한 결함 회복 성능을 보인다. 따라서 SIOS를 결함허용정보 저장 장치로 사용하는 클러스터 시스템을 설계할 경우, SIOS 구성에 참여하는 노드 수가 클러스터 시스템의 결함 회복 성능을 결정하는 데에 중요한 요소가됨을 알 수 있다.

Improving Performance of Human Action Recognition on Accelerometer Data (가속도 센서 데이터 기반의 행동 인식 모델 성능 향상 기법)

  • Nam, Jung-Woo;Kim, Jin-Heon
    • Journal of IKEEE
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    • v.24 no.2
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    • pp.523-528
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    • 2020
  • With a widespread of sensor-rich mobile devices, the analysis of human activities becomes more general and simpler than ever before. In this paper, we propose two deep neural networks that efficiently and accurately perform human activity recognition (HAR) using tri-axial accelerometers. In combination with powerful modern deep learning techniques like batch normalization and LSTM networks, our model outperforms baseline approaches and establishes state-of-the-art results on WISDM dataset.

User Behavior Based Web Attack Detection in the Face of Camouflage (정상 사용자로 위장한 웹 공격 탐지 목적의 사용자 행위 분석 기법)

  • Shin, MinSik;Kwon, Taekyoung
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.31 no.3
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    • pp.365-371
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    • 2021
  • With the rapid growth in Internet users, web applications are becoming the main target of hackers. Most previous WAFs (Web Application Firewalls) target every single HTTP request packet rather than the overall behavior of the attacker, and are known to be difficult to detect new types of attacks. In this paper, we propose a web attack detection system based on user behavior using machine learning to detect attacks of unknown patterns. In order to define user behavior, we focus on features excluding areas where an attacker can camouflage as a normal user. The experimental results shows that by using the path and query information to define users' behaviors, best results for an accuracy of 99% with Decision forest.

Robust Head Pose Estimation for Masked Face Image via Data Augmentation (데이터 증강을 통한 마스크 착용 얼굴 이미지에 강인한 얼굴 자세추정)

  • Kyeongtak, Han;Sungeun, Hong
    • Journal of Broadcast Engineering
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    • v.27 no.6
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    • pp.944-947
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    • 2022
  • Due to the coronavirus pandemic, the wearing of a mask has been increasing worldwide; thus, the importance of image analysis on masked face images has become essential. Although head pose estimation can be applied to various face-related applications including driver attention, face frontalization, and gaze detection, few studies have been conducted to address the performance degradation caused by masked faces. This study proposes a new data augmentation that synthesizes the masked face, depending on the face image size and poses, which shows robust performance on BIWI benchmark dataset regardless of mask-wearing. Since the proposed scheme is not limited to the specific model, it can be utilized in various head pose estimation models.

A Wavelet-based Blind Watermarking Scheme Using Pixel Correlation of Low Sub-band (저주파 대역의 픽셀 상관도를 이용한 웨이블릿 기반 블라인드 워터마킹 기법)

  • Yoo, Kil-Sang;Jahng, Sung-Gahb;Lee, Won-Hyung
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.9C
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    • pp.1298-1305
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    • 2004
  • Most watermarking techniques embed watermarks in the middle frequency range for robustness and invisibility. In our proposed watermarking algorithms embed the gaussian sequence watermark into low frequency area of the wavelet transform domain because the histogram of low sub-band area is composed by similar coefficients. Also, our proposed scheme doesn't need the original image in extraction procedure The experimental results show good robustness against the Check Mark benchmarking tools.

Improved Simulated-Annealing Technique for Sequence-Pair based Floorplan (Sequence-Pair 기반의 플로어플랜을 위한 개선된 Simulated-Annealing 기법)

  • Sung, Young-Tae;Hur, Sung-Woo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.4
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    • pp.28-36
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    • 2009
  • Sequence-Pair(SP) model represents the topological relation between modules. In general, SP model based floorplanners search solutions using Simulated-Annealing(SA) algorithm. Several SA based floorplanning techniques using SP model have been published. To improve the performance of those techniques they tried to improve the speed for evaluation function for SP model, to find better scheduling methods and perturb functions for SA. In this paper we propose a two phase SA based algorithm. In the first phase, white space between modules is reduced by applying compaction technique to the floorplan obtained by an SP. From the compacted floorplan, the corresponding SP is determined. Solution space has been searched by changing the SP in the SA framework. When solutions converge to some threshold value, the first phase of the SA based search stops. Then using the typical SA based algorithm, ie, without using the compaction technique, the second phase of our algorithm continues to find optimal solutions. Experimental results with MCNC benchmark circuits show that how the proposed technique affects to the procedure for SA based floorplainning algorithm and that the results obtained by our technique is better than those obtained by existing SA-based algorithms.

A Multistriped Checkpointing Scheme for the Fault-tolerant Cluster Computers (다중 분할된 구조를 가지는 클러스터 검사점 저장 기법)

  • Chang, Yun-Seok
    • The KIPS Transactions:PartA
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    • v.13A no.7 s.104
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    • pp.607-614
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    • 2006
  • The checkpointing schemes should reduce the process delay through managing the checkpoints of each node to fit the network load to enhance the performance of the process running on the cluster system that write the checkpoints into its global stable storage. For this reason, a cluster system with single IO space on a distributed RAID chooses a suitable checkpointng scheme to get the maximum IO performance and the best rollback recovery efficiency. In this paper, we improved the striped checkpointing scheme with dynamic stripe group size by adapting to the network bandwidth variation at the point of checkpointing. To analyze the performance of the multi striped checkpointing scheme, we applied Linpack HPC benchmark with MPI on our own cluster system with maximum 512 virtual nodes. The benchmark results showed that the multistriped checkpointing scheme has better performance than the striped checkpointing scheme on the checkpoint writing efficiency and rollback recovery at heavy system load.

A Representative Pattern Generation Algorithm Based on Evaluation And Selection (평가와 선택기법에 기반한 대표패턴 생성 알고리즘)

  • Yih, Hyeong-Il
    • Journal of the Korea Society of Computer and Information
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    • v.14 no.3
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    • pp.139-147
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    • 2009
  • The memory based reasoning just stores in the memory in the form of the training pattern of the representative pattern. And it classifies through the distance calculation with the test pattern. Because it uses the techniques which stores the training pattern whole in the memory or in which it replaces training patterns with the representative pattern. Due to this, the memory in which it is a lot for the other machine learning techniques is required. And as the moreover stored training pattern increases, the time required for a classification is very much required. In this paper, We propose the EAS(Evaluation And Selection) algorithm in order to minimize memory usage and to improve classification performance. After partitioning the training space, this evaluates each partitioned space as MDL and PM method. The partitioned space in which the evaluation result is most excellent makes into the representative pattern. Remainder partitioned spaces again partitions and repeat the evaluation. We verify the performance of Proposed algorithm using benchmark data sets from UCI Machine Learning Repository.