• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.997-999
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• 2005

In order for efficient Bluetooth Baseband functional test, Bluetooth SIG (Special Interest Group) provides with Test Suite Structure (TSS) in the Bluetooth specification version 1.1. Bluetooth Baseband hardware which needs to be authenticated should implement the test specification defined in the TSS part I.1 through I.3. In this paper, we discuss the method to verify and test a Bluetooth Baseband implementation based on the TSS version 1.0. Also, we describe various senario and implementation possibilities to perform the Bluetooth Baseband authentication test.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.1000-1002
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• 2005

In the Bluetooth piconet in which up to 7 slave devices can be connected simultaneously at one network instance, the wireless data expected to be sent over to the RF interface should be sliced by the unit of 1 micrometer, which is a requirement in the specification of the Bluetooth version 1.1. In this contribution, we have designed a digital low-pass filter which is able to slice the unstable analog signal fed from the RF interface to the Baseband, by the uniform unit of 1 micrometer, and is also capable of removing the possible noise which can be caused by the analog circuit system. The low-pass filter operated well in the various modes of the Bluetooth RF embedded Baseband chip such as sleep mode, normal mode, and high-speed mode at 12MHz, 24MHz, and 48MHz respectively.

• Electronics and Telecommunications Trends
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• v.28 no.2
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• pp.58-69
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• 2013

LTE 기반의 펨토셀 활용과 개발에 대한 요구는 LTE로의 이동통신 서비스가 본격화되면서, 최근 몇 년간 중요한 이슈로 자리매김하고 있다. 기지국 장비의 재설치와 주파수의 효율적인 활용 측면에서 펨토셀 기지국은 이동통신 서비스 사업자와 가입자에게 동시에 중요한 역할을 수행할 것으로 보인다. 이러한 펨토셀 기지국의 필요성을 충족시켜 주기 위해서는 펨토셀 기지국의 형상과 기능에서 그 본래의 요구를 만족시켜 주는 것이 중요하다. 무엇보다도, LTE 기반의 펨토셀 기지국은 기기의 간편한 설치와 매크로셀 기지국의 오프로딩이라는 역할을 충실히 수행할 수 있는지가 핵심적 평가 요소가 될 것이다. 이를 위해서는 펨토셀 기지국의 핵심 부품인 베이스밴드 SoC(System on a Chip) 성능 및 기능이 펨토셀 기지국 전체의 경쟁력을 판단하는 데 중요한 척도 중에 하나가 될 것이다. 본고에서는 이러한 관점에서 ETRI가 개발한 LTE 펨토셀 기지국의 베이스밴드 SoC를 중심으로 그 형상과 개발 과정을 기술하고 해외 업체들의 베이스밴드 칩셋의 형상과 개발상황에 대해서 자세히 기술하기로 한다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.38-44
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• 2008

In this paper, we introduce an low complexity and low power IR-UWB (impulse radio ultra wideband) baseband transceiver for wireless sensor network. The proposed baseband, implemented by TSMC 0.18um CMOS technology, has a simple structure in which a simplified packet structure and a digital synchronizer with 1-bit sampler to detect incoming pulses are used. Besides, clock gating method using gated clock cell as well as customized clock domain division can reduce the total power consumption drastically. As a result, the proposed baseband has about 23K digital gates with an internal memory of 2Kbytes and achieves about 1.8mW@1Mbps power consumption.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.681-684
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• 2008

Bluetooth baseband performs FEC (forward error check) at the interface of transmitter and receiver modem. Well-designed FEC means directly the efficiency of retransmission of the data payload therefore design optimization is very important. In this paper, we designed a optimal 1/3, 2/3 type of FEC. 1/3 FEC. which performs 3 times customary repetition was designed for packet header, and 2/3 FEC was designed for data packets with (15, 10) reduced hamming code. The proposed hardware FEC block was described and verified using Verilog HDL and later to be automatically synthesized. The synthesized FEC block operated at 40Mhz normal clock speed of the target baseband microcontroller.

• Proceedings of the Korea Multimedia Society Conference
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• 2001.11a
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• pp.30-34
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• 2001

본 논문에서는 근거리에 놓여있는 노트북, 휴대폰, PDA, 혜드셋 등 각종 이동 가능한 장치들을 하나의 무선네트워크로 연결할 수 있는 블루투스의 베이스밴드 시스템 프로토콜 기능을 분석하고 설계하였다. 즉, 전체적인 논리 기능구조를 설계한 후 하드웨어로 구현될 패킷생성 블록, HEC와 CRC 기능블륵, Whitening/Dewhitening 기능블록, FEC 기능블록, 입출력 블록(TX, RX 루틴), 클럭 생성 기능블록, 주파수 선별 기능블록, 오디오 기능블록 그리고, 패킷 제어 블록들의 처리절차를 Verilog HDL 코드로 설계 및 검증하였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.6 no.4
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• pp.45-47
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• 1969

mm파 IMPATT발진기의 변조감도, 선형성 및 FM 잡음이 기술되었다. 발진기가 FM을 단상승시간 펄스로서 변조되게 할 때 검파된 FM펄스는 원래 변조하는 베이스 밴드 펄스와 비교하여 거의 왜곡이 없음을 나타내었다.

• Journal of Astronomy and Space Sciences
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• v.23 no.4
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• pp.445-452
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• 2006

In this paper, the conceptual design of satellite digital base put which is based upon data interface between satellite on-board computer and remote devices like satellite sub-components is presented. This conceptual design shows the unification of the interface between on-board computer and satellite remote devices and the hierarchical results of the interface level. A comparison of different system and merits and demerits of digital base part coming from this conceptual design is performed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.903-906
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• 2009

In this contribution, we designed a serial port interface (SPI) suitable for embedded systems, especially for Bluetooth baseband. Proposed architecture is compatible for the APB bus in AMBA bus architecture. The 8-bit design of the SPI module is in charge of transferring the data and the instructions between the external devices and the coprocessors. We adopted the cyclic redundancy check method for the error correction. Also, we provided the interface for multimedia cards. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.673-676
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• 2008

In wireless communications such as Bluetooth, Baseband should be able to minimize the DC bias of the data which passed the modem interface of either transmitter or receiver for the reliability of the circuit and the integrity of the data. The transmitter scrambles the data to send randomly to the error correction block and the receiver recovers the randomly spread data as they have been. To design the whitening block, it is important to select the prime polynomial for the filtering. In this paper, we designed a optimal whitening block using the prime polynomial $g(D)=D^7+D^4+1$ for hardware and area efficiency. The proposed hardware whitening block was described and verified using Verilog HDL and later to be automatically synthesized. The synthesized whitening block operated at 40Mhz normal clock speed of the target baseband microcontroller.