• ETRI Journal
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• v.10 no.3
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• pp.83-91
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• 1988

This paper describes the architecture and the performance analysis of a multiprocessor system, which is based on the shared memory and single system bus. The system bus provides the pended protocol for the multiprocessor environment. Analyzing the processor utilization, address/data bus utilization and memory conflicts, we use a simulation model. The hit ratio of private cache memory is a major factor on the linear increase of the performance of a shared memory based multiprocessor system.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.237-238
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• 2007

국내 산업현장에서 공장시스템들을 효율적이고 유기적으로 연결시키기 위해서 산업네트워크인 산업용 프로토콜을 활용한다. 그중에서도 국내 굴지의 석유화학 공정에서는 Modbus Protocol을 사용하고 있다. 하지만 이에 대한 연구가 국내에서는 매우 열악하여 제대로 된 정보를 찾기 힘들다. 이에 국내 산업환경에서 활용하는 모드버스 프로토콜을 개선하여 이를 현장에 적용하는 연구를 하게되었다. 이전 연구에서는 모드버스 프로토콜 개선을 위해서 캐쉬 기법을 적용하여 탱크 데이터 처리 시간을 단축시키는 결과를 도출하였으며 이를 이용하여 석유화학 공정 탱크의 교체시기를 판별하였다. 이번에는 모드버스 캐쉬 기법을 이용하여 탱크사용 예측과 하드닝 기법을 적용한 탱크 테이터예측 알고리즘을 설계하고 이를 시뮬레이션 결과를 소개하고자 한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.60-60
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• 2001

칩과 칩 사이의 전송 속도가 증가함에 따라, 누화 및 스위칭 잡음에 의한 시스템의 성능 저하가 심각해지고 있다. 본 논문에서 제안하는 인터페이스는 한 심벌 펄스의 상승/하강 에지 위치에 데이터를 엔코딩하고, 천이 방향이 반대인 P-CTR과 N-CTR (positive/Negative Constant Transition Rate)을 사용하며, P-CTR 드라이버 2개 묶음과 N-CTR 드라이버 2개 묶음을 교대로 배치하여 버스를 구성한다. 제안하는 P/N-CTR 코드 인터페이스에서는 임의의 한 배선에 대해서 양옆의 이웃한 배선 신호가 동시에 같은 방향으로 스위칭하는 경우가 발생하지 않기 때문에 최대 누화 잡음과 최대 스위칭 잡음을 기존의 I/O 인테페이스 보다 감소시킬 수 있다. 제안하는 인터페이스 방식의 잡음 감소 특성을 검증하기 위하여 다양한 배선 구조와 여러 비트 폭의 버스 구조에 적용하고, 0.35㎛ SPICE 파라미터를 이용한 HSPICE 시뮬레이션을 수행하였다. 제안한 인터페이스는 기존의 인터페이스와 비교하여 32 비트 미만의 버스에서는 최대 누화 잡음이 최소26.78 % 감소하고, 누화는 50 % 감소한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1401-1411
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• 1999

Due to the increase of multimedia services, multicasting is considered as important design factor for ATM switch. To resolve the traffic expansion problem that is occurred by multicast in multistage interconnection networks, this paper proposes the multicast switch using a high-speed bus and a shared memory switch. Since the proposed switch uses a high-speed time division bus as a connection medium and chooses a shared memory switch as a basic switch module, it provides good port scalability. The traffic arbitration scheme enables internal non-blocking. By simulation we proves a good performance in the data throughput and the cell delay.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.50-56
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• 2009

SoC(System on a Chip) has several masters, slaves, arbiter and decoder in bus architecture. Master initiates the data transactions like CPU, DMA and DSP and slave responses the data transactions like SRAM SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, SoC performance can be changed definitely. Fixed priority, round-robin, TDM arbitration are used in general arbitration method, In this study, we compose TLM algorithm and analyze general arbitration methods through TLM simulation. Consequently, we propose the hybrid bus arbitration policy and verify the performance, compared with the other arbitration methods.

• Journal of Cadastre & Land InformatiX
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• v.52 no.2
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• pp.171-187
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• 2022

Recently, the demand and development for non-face-to-face services are rapidly progressing due to the pandemic caused by the COVID-19, and attention is focused on the metaverse at the center. Entering the era of the 4th industrial revolution, Metaverse, which means a world beyond virtual and reality, combines various sensing technologies and 3D reconstruction technologies to provide various information and services to users easily and quickly. In particular, due to the miniaturization and economic increase of convergence sensors such as unmanned aerial vehicle(UAV) capable of high-resolution imaging and high-precision LiDAR(Light Detection and Ranging) sensors, research on digital-Twin is actively underway to create and simulate real-life twins. In addition, Game engines in the field of computer graphics are developing into metaverse engines by expanding strong 3D graphics reconstuction and simulation based on dynamic operations. This study constructed a mirror-world type metaverse that reflects real-world coordinate-based reality using Unreal Engine 5, a recently announced metaverse engine, with accurate 3D spatial information data of convergence sensors based on unmanned aerial system(UAS) and LiDAR. and then, spatial information contents and simulations for users were produced based on various public data to verify the accuracy of reconstruction, and through this, it was possible to confirm the construction of a more realistic and highly utilizable metaverse. In addition, when constructing a metaverse that users can intuitively and easily access through the unreal engine, various contents utilization and effectiveness could be confirmed through coordinate-based 3D spatial information with high reproducibility.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.24-31
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• 2007

Up to date, a lot of bus protocol and bus architecture are released though most of them are based on the shared bus architecture and inherit the limitation of performance. SNP (SoC Network Protocol), and hence, SNA (SoC Network Architecture) which are high performance on-chip-bus protocol and architecture, respectively, have been proposed to solve the problems of the conventional shared bus. We refine the SNA specification and improve the performance and functionality. The performance of the SNA is improved by supporting simultaneous routing for bus request of multiple masters. The internal routing logic is also improved so that the gate count is decreased. The proposed SNA employs XSNP (extended SNP) that supports almost perfect compatibility with AMBA AHB protocol without performance degradation. The hardware complexity of the improved SNA is not increased much by optimizing the current routing logic. The improved SNA works for IPs with the original SNP at its best performance. In addition, it can also replace the AMBA AHB or interconnect matrix of a system, and it guarantees simultaneous multiple channels. That is, the existing AMBA system can show much improved performance by replacing the AHB or the interconnect matrix with the SNA. Thanks to the small number of interconnection wires, the SNA can be used for the off-chip bus system, too. We verify the performance and function of the proposed SNA and XSNP simulation and emulation.

• Journal of Korean Society of Transportation
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• v.23 no.3 s.81
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• pp.35-47
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• 2005

This paper is to review a literature concerning Bus Transit Route Network Design(BTRNDP), to describe a future study direction for a systematic application for the BTRNDP. Since a bus transit uses a fixed route, schedule, stop, therefore an approach methodology is different from that of auto network design problem. An approach methodology for BTRNDP is classified by 8 categories: manual & guideline, market analysis, system analytic model. heuristic model. hybrid model. experienced-based model. simulation-based model. mathematical optimization model. In most previous BTRNDP, objective function is to minimize user and operator costs, and constraints on the total operator cost, fleet size and service frequency are common to several previous approach. Transit trip assignment mostly use multi-path trip assignment. Since the search for optimal solution from a large search space of BTRNDP made up by all possible solutions, the mixed combinatorial problem are usually NP-hard. Therefore, previous researches for the BTRNDP use a sequential design process, which is composed of several design steps as follows: the generation of a candidate route set, the route analysis and evaluation process, the selection process of a optimal route set Future study will focus on a development of detailed OD trip table based on bus stop, systematic transit route network evaluation model. updated transit trip assignment technique and advanced solution search algorithm for BTRNDP.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2433-2438
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• 2011

Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, bus system performance can be changed definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this study, we proposed the score arbitration method and synthesized it using Hynix 0.18um technology, after design of RTL. Also we analyze the performance compared with general arbitration methods through simulation.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.15 no.6
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• pp.62-70
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• 2016

Increased bus traffic leads inefficiency at near-side bus stops in median exclusive bus lane because buses are waiting for a signal does not have a vehicle arrived. This study suggests a method for estimating a proper spacing between bus stops and signalized intersection to prevent the inefficiency. We modified the Poisson model for a proper spacing by using both dwell time and waiting time of signal instead of using dwell time only. The waiting time of signal changes by spacing and it was measured using micro simulation program. The iterative algorithm using the change of waiting time of signal was also suggested. By applying the proposed method, measure waiting time by simulation and iterative algorithm, the spacing of near-side bus stops, proper spacing is suggested according to flow rate level.