• Title/Summary/Keyword: 밴드갭 기준 전압

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Wide Tuning Range Varactor Diodeless LC-tank VCO (Miller 커패시터를 이용한 넓은 가변 범위의 LC-tank 전압 제어 발진기)

  • Ryu, J.Y.;Ryu, S.T.;Jung, S.H.;Cho, G.H.
    • Proceedings of the KIEE Conference
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    • 2001.07d
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    • pp.2579-2581
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    • 2001
  • 넓은 가변 범위를 가지는 LC 탱크 전압 제어 발진기에 관해 본 논문에서 소개하고자 한다. LC 탱크 전압 제어 발진기의 발진을 소멸시키는 밀러 증폭기의 ESR을 제거함으로써 넓은 가변 범위를 얻을 수 있다. LC 탱크 전압 제어 발진기는 발진기 코어와 버퍼, 밴드갭(bandgap) 기준 전압 발생기 그리고 드라이브 증폭기로 구성되어 있다. 발진기 코어는 1.3mA의 전류를 소모하고 약 1GHz의 가변 범위를 가진다. 출력주파수의 가변 범위내에 발진기의 출력 전력은 3dBm 이내로 변한다. 이러한 LC 탱크 전압 제어 발진기는 BiCMOS 공정을 이용하여 제작되었고 2.7V 단일 전원에서 31.5mW의 전력을 소모한다.

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Design of Temperature System Using BiCMOS (BiCMOS를 이용한 온도 센서 시스템의 설계)

  • 최진호
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.52 no.8
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    • pp.330-334
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    • 2003
  • A Temperature sensor system in which the digital output signal is proportional to the operating temperature is designed. The temperature sensor system is designed by using BiCMOS technology and consists of temperature sensor, voltage-to-frequency converter and counter. The proposed temperature sensor system has error less than $1^{\circ}C$ in the temperature range $-25^{\circ}C$ to $55^{\circ}C$.

Design of Low-Voltage Reference Voltage Generator for NVM IPs (NVM IP용 저전압 기준전압 회로 설계)

  • Kim, Meong-Seok;Jeong, Woo-Young;Park, Heon;Ha, Pan-Bong;Kim, Young-Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.375-378
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    • 2013
  • A reference voltage generator which is insensitive to PVT (process-voltage-temperature) variation necessary for NVM memory IPs such as EEPROM and MTP memories is designed in this paper. The designed BGR (bandgap reference voltage) circuit based on MagnaChip's $0.18{\mu}m$ EEPROM process uses a low-voltage bandgap reference voltage generator of cascode current-mirror type with a wide swing and shows a reference voltage characteristic insensitive to PVT variation. The minimum operating voltage is 1.43V and the VREF sensitivity against VDD variation is 0.064mV/V. Also, the VREF sensitivity against temperature variation is $20.5ppm/^{\circ}C$. The VREF voltage has a mean of 1.181V and its three sigma ($3{\sigma}$) value is 71.7mV.

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Design of PFM Boost Converter with Dual Pulse Width Control (이중 펄스 폭을 적용한 PFM 부스트 변환기 설계)

  • Choi, Ji-San;Jo, Yong-Min;Lee, Tae-Heon;Yoon, Kwang-Sub
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.40 no.9
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    • pp.1693-1698
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    • 2015
  • This paper proposed a PFM(pulse-frequency modulator) boost converter which has dual pulse-width. The PFM boost converter is composed of BGR(band gap voltage reference generating circuit), voltage reference generating circuit, soft-start circuit, error amplifier, high-speed comparator, inductor current sensing circuit and pulse-width generator. Converter has different inductor peak current so it has wider load current range and smaller output voltage ripple. Proposed PFM boost converter generates 18V output voltage with input voltage of 3.7V and it has load current range of 0.1~300mA. Simulation results show 0.43% output voltage ripple at ligh load mode and 0.79% output voltage ripple at heavy load mode. Converter has efficiency 85% at light lode mode and it has maximum 86.4% at 20mA load current.

Design of a LDO regulator with a protection Function using a 0.35 µ BCD process (0.35 ㎛ BCD 공정을 이용한 보호회로 기능이 추가된 모바일용 LDO 레귤레이터)

  • Lee, Min-Ji;Son, Hyun-Sik;Park, Young-Soo;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.1
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    • pp.627-633
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    • 2015
  • We designed of a LDO regulator with a OVP and UVLO protection function for a PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. The proposed LDO regulator is designed for low voltage input power protection. Proposed LDO circuit generated fixed 2.5 V from a supply of 3.3V. It was designed with 3.3 V power supply using a $0.35{\mu}m$ CMOS technology. SPICE simulation results showed that the proposed circuit provides 0.713 mV/V line regulation with output 2.5 V ~ 3.9 V and $8.35{\mu}V/mA$ load regulation with load current 0 mA to 40 mA.

Reviews and Proposals of Low-Voltage DRAM Circuit Design (저전압 DRAM 회로 설계 검토 및 제안)

  • Kim, Yeong-Hui;Kim, Gwang-Hyeon;Park, Hong-Jun;Wi, Jae-Gyeong;Choe, Jin-Hyeok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.4
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    • pp.251-265
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    • 2001
  • As the device scaling proceeds, the operating voltage(VDD) of giga-bit DRAMs is expected to be reduced to 1.5V or down, fir improving the device reliability and reducing the power dissipation. Therefore the low-voltage circuit design techniques are required to implement giga-bit DRAMs. In this work, state-of-art low-voltage DRAM circuit techniques are reviewed, and four kinds of low-voltage circuit design techniques are newly proposed for giga-bit DRAMs. Measurement results of test chips and SPICE simulation results are presented for the newly proposed circuit design techniques, which include a hierarchical negative-voltage word-line driver with reduced subthreshold leakage current, a two-phase VBB(Back-Bias Voltage) generator, a two-phase VPP(Boosted Voltage) generator and a bandgap reference voltage generator.

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Design of a Low Drop-out Regulator with a UVLO Protection Function (UVLO 보호기능이 추가된 LDO 레귤레이터 설계)

  • Park, Won Kyeong;Lee, Su Jin;Park, Yong Su;Song, Han Jung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.10
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    • pp.239-244
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    • 2013
  • This paper presents a design of the CMOS LDO regulator with a UVLO protection function for a high speed PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. UVLO block between the power transistor and the power supply is added for a low input protection function. Also, UVLO block showed normal operation with turn-off voltage of 2.7V and turn-on voltage of 4 V in condition of 5 V power supply. Proposed circuit generated fixed 3.3 V from a supply of 5V. From SPICE simulation results using a $1{\mu}m$ high voltage CMOS technology, simulation results were 5.88 mV/V line regulation and 27.5 uV/mA load regulation with load current 0 mA to 200 mA.

Design of BiCMOS Signal Conditioning Circuitry for Piezoresistive Pressure Sensor (압저항형 압력센서를 위한 BiCMOS 신호처리회로의 설계)

  • Lee, Bo-Na;Lee, Moon-Key
    • Journal of Sensor Science and Technology
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    • v.5 no.6
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    • pp.25-34
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    • 1996
  • In this paper, we have designed signal conditioning circuitry for piezoresistive pressure sensor. Signal conditioning circuitry consists of voltage reference circuit for sensor driving voltage and instrument amplifier for sensor signal amplification. Signal conditioning circuitry is simulated using HSPICE in a single poly double metal $1.5\;{\mu}m$ BiCMOS technology. Simulation results of band-gap reference circuit showed that temperature coefficient of $21\;ppm/^{\circ}C$ at the temperature range of $0\;{\sim}\;70^{\circ}C$ and PSRR of 80 dB. Simulation results of BiCMOS amplifier showed that dc voltage gain, offset voltage, CMRR, CMR and PSRR are outperformed to CMOS and Bipolar, but power dissipation and noise voltage were more improved in CMOS than BiCMOS and Bipolar. Designed signal conditioning circuitry showed high input impedance, low offset and good CMRR, therefore, it is possible to apply sensor and instrument signal conditioning circuitry.

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A Integrated Circuit Design of DC-DC Converter for Flat Panel Display (플랫 판넬표시장치용 DC-DC 컨버터 집적회로의 설계)

  • Lee, Jun-Sung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.10
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    • pp.231-238
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    • 2013
  • This paper describes a DC-DC converter IC for Flat Panel Displays. In case of operate LCD devices various type of DC supply voltage is needed. This device can convert DC voltage from 6~14[V] single supply to -5[V], 15[V], 23[V], and 3.3[V] DC supplies. In order to meet current and voltage specification considered different type of DC-DC converter circuits. In this work a negative charge pump DC-DC converter(-5V), a positive charge pump DC-DC converter(15V), a switching Type Boost DC-DC converter(23V) and a buck DC-DC converter(3.3V). And a oscillator, a thermal shut down circuit, level shift circuits, a bandgap reference circuits are designed. This device has been designed in a 0.35[${\mu}m$] triple-well, double poly, double metal 30[V] CMOS process. The designed circuit is simulated and this one chip product could be applicable for flat panel displays.

A Temperature- and Supply-Insensitive 1Gb/s CMOS Open-Drain Output Driver for High-Bandwidth DRAMs (High-Bandwidth DRAM용 온도 및 전원 전압에 둔감한 1Gb/s CMOS Open-Drain 출력 구동 회로)

  • Kim, Young-Hee;Sohn, Young-Soo;Park, Hong-Jung;Wee, Jae-Kyung;Choi, Jin-Hyeok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.8
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    • pp.54-61
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    • 2001
  • A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage ($V_OL$) to be equal to the reference voltage ($V_{OL.ref}$) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1Gb/s. The worst-case variations of $V_{OL.ref}$ and $V_OL$ of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of $20^{\circ}C$ to $90^{\circ}C$ and a supply voltage range of 2.25V to 2.75V, while the worst-case variation of $V_OL$ of the conventional output driver was measured to be 24% at the same temperature and supply voltage ranges.

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