• Journal of the Semiconductor & Display Technology
• /
• v.20 no.3
• /
• pp.146-151
• /
• 2021

We introduce an arbitrary waveform generation method and its H/W implementation case based on Rademacher and Walsh function. According to the orthogonal and periodic features of Rademacher and Walsh function, simple calculations can generate arbitrary waves with affordable logics. We implemented an FPGA-based AWS using above two functions, and verified. HDL simulation shows the proposed idea can draw desired analog test waveforms very fast, and its H/W size is promising to Built-Out Self-Test(BOST) logics for AI ICs.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.37 no.4
• /
• pp.35-46
• /
• 2000

Semiconductor technology includes from semiconductor materials, design, fabrication, handling of process equipments, reliability test to packaged semiconductor devices. Our departmental curriculum is organized with 2-years/6-quarters system of Ulsan College: the understanding for the fundamental of semiconductor is carried out in the first academic year and the training for the design skill on semiconductor devices will be focused in the second academic year. The main focus is reflected on the worldwide trend on the design engineering of semiconductor devices and considered for the market establishment on design engineers trained by the lab-oriented practice as well as the fundamental of semiconductor technology.

• Proceedings of the Korean Information Science Society Conference
• /
• 2012.06a
• /
• pp.74-76
• /
• 2012

반도체 공정은 웨이퍼를 제작할 때 오류가 발생할 경우 웨이퍼 전체를 사용하지 못하는 손실이 발생한다. 이로 인해 반도체 공정제어 소프트웨어는 높은 품질을 요구하고 있다. 반도체 공정제어 소프트웨어를 위한 테스트의 중요성도 높아졌다. 하지만 반도체 공정제어 공정제어 소프트웨어 테스트는 대상이 되는 프로그램에 따라 테스트 스크립트의 변화가 많다. 이로 인해 테스트 스크립트 작성의 비용이 높으며, 이미 작성된 스크립트의 재사용이 어렵다. 이러한 문제를 해결하기 위해 이 논문에서는 반도체 공정제어 소프트웨어를 위한 테스트 스크립트 생성과정과 생성된 스크립트의 재사용성을 높이기 위한 색인방법을 제안한다. 제안한 스크립트 생성과정은 반도체 공정제어에서 사용하는 일반적인 테스트 과정을 기반으로 스크립트 생성의 복잡도를 줄일 수 있다. 소프트웨어에 존재하는 함수의 수정으로 인한 스크립트 재사용성 불가 문제를 해결하기 위해 함수에 대한 정보를 색인하여 기존 스크립트의 재사용성을 높인다.

• Journal of the Semiconductor & Display Technology
• /
• v.2 no.2
• /
• pp.25-30
• /
• 2003

In the case of a vibration sensitive equipment, it require a vibration free environment to provide its proper function. Especially, lithography and inspection device, which have sub-nanometer class high accuracy and resolution, have come to necessity for producing more improved Giga Class semi conductor wafers. This high technology equipments require very strict environmental vibration criteria in proportion to the accuracy of the manufacturing. In this paper, the dynamic analysis and modal test were performed to evaluate the dynamic properties of the constructing clean room structure. Based on these results, a structural dynamic modification(SDM) were required to satisfiy the vibration allowable limit for pression machine. Therefore, in order to improve the dynamic stiffness of clean room structure, the VSD system which can control the force applied on structure, were adopted and its utility were proved from dynamic test results of the improved structure after a modification work.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.360-360
• /
• 2010

반도체 산업은 지속적인 design rule 감소로 인해 직접도 및 Pin Count가 점점 증가함에 따라 보증해야할 회로의 수와 기능이 더불어 증가하고 있으며, 그 중 Test Cost 감소 방법 확보가 시급하게 되었다. 이에 따라 Test Cost 감소와 직결된 Test Time 감소 방법이 다양하게 제시되고 연구되고 있다. 본 논문은 Test Time의 한 부분인 반도체 검사 장비 (Automatic Test Equipment)의 효율적인 제어 방법을 제공함으로써, 관련 분야의 이해를 돕고자 한다.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.15 no.10
• /
• pp.5906-5911
• /
• 2014

Currently, there are many processes of package assembly and inspections of real fields that examine whether a manufactured semiconductor can be operated regularly and can endure low humidity or high temperatures. As the inspection equipment of a semiconductor test handler picker has been used at the inspection process, these inspection equipment frames were modelled in 3D and these models were analyzed using 3 kinds of fatigue loadings. As the analysis result, maximum deformation occurred at the midparts of the frames at cases 1 and 2. Among the cases of nonuniform fatigue loads, the 'SAE bracket history' with the severest change in load became the most unstable but the 'Sample history' became the most stable. Fatigue analysis result can be used effectively with the design of an inspecting equipment frame of a semiconductor test handler picker to examine the prevention and durability against damage.

• Journal of the Semiconductor & Display Technology
• /
• v.18 no.3
• /
• pp.42-46
• /
• 2019

In this paper, we introduce the novel idea to improve parallel test efficiency of semiconductor test. The idea includes the test interface card consisting of NoC structure able to transmitting test data regardless of ATE speed. We called the scheme "Multi-Clock" mode. In the proposed mode, because NoC can spread over the test data in various rates, many semiconductors are tested in the same time. We confirm the proposed idea will be promising through a FPGA board test and it is important to find a saturation point of the Multi-Clock mode due to the number of test chips and ATE channels.

• Journal of the Semiconductor & Display Technology
• /
• v.19 no.2
• /
• pp.82-87
• /
• 2020

In this paper, we introduce the novel idea to improve the B/W usage efficiency of on-chip networks used for TAM to test multiple DRAMs. In order to avoid the local bottleneck of test packets caused by an ATE, we make test patterns using microcode-based instructions within ATE and adopt a test bus to transmit test responses from DRAM DFT (Design for Testability) called Test Generator (TG) to ATE. The proposed test platform will contribute to increasing the test economics of memory IC industry.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2012.04a
• /
• pp.850-853
• /
• 2012

반도체 산엽에서 제조공정상의 웨이퍼 가공시에 여러 가지 화학물질을 사용하고 있으며, 제조공정상 유해가스의 발생 빈도수가 높다. 반도체 제품을 생산하기 위한 공정 모니터링 사스템은 관리실에서만 가스 누출여부, 온습도 변화 및 영상을 모니터링 하고 있으며, 관리자가 자리를 비우게 되면, 반도체 제품 생산공정에 발생하는 긴급 상황에 대응하기 어렵다. 본 논문에서는 반도체 공정 모니터링 테스트 베드에서는 반도체 생산 공정의 온도, 습도 및 가스 누출 여부와 같은 주변환경을 모바일에서 모니터링 및 즉각적인 상황 대응이 가능한 공정 모니터링을 연구 하였다.

• Journal of the Semiconductor & Display Technology
• /
• v.2 no.4
• /
• pp.1-7
• /
• 2003

In this paper, we design the pattern generator circuits using PLDs(Programmable Logic Devices). The pattern generator is the circuit which generates the test pattern signal for the inspection of logical defects of semiconductor products. The proposed circuits are designed by the PLD design tool(MAX+ II of ALTERA). Also the designed circuits are simulated for the verification of the designed ones. The simulation results have a good performance.