• Proceedings of the Korean Society of Computer Information Conference
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• 2014.01a
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• pp.271-272
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• 2014

현재 디지털 시스템 설계가 필요한 모든 유한 상태머신을 설계에는 필수적 밀리 모델이나 무어 모델이 들어간다. 그러나 각각의 기기와 기능에 따라서 밀리 모델과 무어 모델 중 어느 모델이 디지털 논리회로 설계에 효율적인지 판단이 모호한 상황이다. 이를 위해 본 논문에서는 유한 상태머신의 하나인 벤딩머신을 대상으로 밀리 모델과 무어 모델을 사용하여 설계한 후, 설계의 복잡도와 구현 게이트 수를 구하여 각 모델의 효율성에 대해 비교 분석하고자 한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.466-468
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• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fired length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.718-723
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• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA. Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fixed length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.327-330
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• 2008

최근 무어의 법칙이 깨짐에 따라 멀티코어 프로세서의 활용이 늘어나고 있으며 이는 임베디드 환경에서도 보편화되었다. 이러한 멀티코어 환경에 기존에 멀티프로세서용으로 개발된 AMP 또는 SMP 구조의 운영체제를 적용시키게 된다면 멀티코어의 장점을 살리기 어렵다. 본 논문에서는 기존 운영체제 구조에 대한 분석을 통해 멀티코어용으로 적합한 운영체제 구조가 가상 머신 구조라는 것을 보이고 있으며 산업에 활용할 수 있는 멀티코어용 가상 머신 모니터의 설계를 제공하고 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1553-1557
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• 2004

A real-time processing system for embedded hardware genetic algorithm is suggested. In order to operate basic module of genetic algorithm in parallel, such as selection, crossover, mutation and evaluation, dual processors based architecture is implemented. The system consists of two Xscale processors and two FPGA with evolvable hardware, which enables to process genetic algorithm efficiently by distributing the computational load of hardware genetic algorithm to each processors equally. The hardware genetic algorithm runs on Linux OS and the resulted chromosome is executed on evolvable hardware in FPGA. Furthermore, the suggested architecture can be extended easily for a couple of connected processors in serial, making it accelerate to compute a real-time hardware genetic algorithm. To investigate the effect of proposed approach, performance comparisons is experimented for an typical computation of genetic algorithm.