• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.4
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• pp.396-404
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• 2011

This paper proposes a performance improvement of a grid-connected wind turbine using sliding-mode based direct power control under an unbalanced grid fault. The proposed control method has some advantages for grid connected control. At first, it doesn't need the synchronous phase angle of the grid voltage. It has also fast dynamic characteristics compared with a conventional current controller. In addition, it is suitable for an unbalance compensation control. The effectiveness and robustness of the proposed algorithm are verified by simulations and experiments.

• Journal of IKEEE
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• v.25 no.1
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• pp.218-228
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• 2021

This paper presents the high-efficiency DC-DC converter using the multi-resonant-circuit. The proposed converter has the power topology of half-bridge and utilizes the multi-resonant-circuit that is composed of 2 inductors (LL) and 1 capacitor (C) to achieve high-efficiency. The multi-resonant-circuit forms each resonant circuit of series circuit type with each resonant frequency, according to the operation modes. This paper first describes the operation pirinciples of proposed converter by the operation modes and steady-state fundamental approximation modelling. Then it shows a design example of the proposed converter based on the principles. And it is validated that the proposed converter has the operation characteristics of high-efficiency DC-DC power conversion through the experimental results of prototype converter implemented by the designed circuit parameters.

• Journal of Broadcast Engineering
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• v.13 no.5
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• pp.732-743
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• 2008

In H.264/AVC, 4$\times$4 block transform is used for intra and inter prediction instead of 8$\times$8 block transform. Using small block size coding, H.264/AVC obtains high temporal prediction efficiency, however, it has limitation in utilizing spatial redundancy. Motivated on these points, we propose a multi-dimensional transform which achieves both the accuracy of temporal prediction as well as effective use of spatial redundancy. From preliminary experiments, the proposed multi-dimensional transform achieves higher energy compaction than 2-D DCT used in H.264. We designed an integer-based transform and quantization coder for multi-dimensional coder. Moreover, several additional methods for multi-dimensional coder are proposed, which are cube forming, scan order, mode decision and updating parameters. The Context-based Adaptive Variable-Length Coding (CAVLC) used in H.264 was employed for the entropy coder. Simulation results show that the performance of the multi-dimensional codec appears similar to that of H.264 in lower bit rates although the rate-distortion curves of the multi-dimensional DCT measured by entropy and the number of non-zero coefficients show remarkably higher performance than those of H.264/AVC. This implies that more efficient entropy coder optimized to the statistics of multi-dimensional DCT coefficients and rate-distortion operation are needed to take full advantage of the multi-dimensional DCT. There remains many issues and future works about multi-dimensional coder to improve coding efficiency over H.264/AVC.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.4
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• pp.77-82
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• 2017

As frequencies increase to the millimeter wave bands the cross sections of wave guides become smaller than a few millimeters, which cause sapatial problems in realization of spatial combining power amplifiers. In this paper we intented to overcome the problem by widening the width of wave guides using horn antenna principles. We designed a widened rectangular wave guide for using in spatial combining power amplifier in 60GHz ISM band(57-64GHz), and we installed Antipodal transition in the widened wave guide, and then we characterized it as a spatial combining power amplifier. For the compatibility of WR15 standard wave guide, we widened the width of WR15 to 7mm using principle of H-plane sectoral horn antenna and then installed 3 slots of back to back Antipodal transition. The designed spatial combining power amplifier showed good characteristics of return loss less than -22.4dB and insertion loss less than 0.53dB. However, as widening the width of the wave guide, additional modes such as $TE_{20}$, $TE_{30}$ in addition to $TE_{10}$ were accurred in the bandwidth of WR15, which restricted the bandwidth and widening of the width of the wave guide.

• Journal of the Korean Society for Nondestructive Testing
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• v.26 no.1
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• pp.18-24
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• 2006

Reactor core and internal structures of a liquid metal reactor (LMR) can not be visually examined due to an opaque liquid sodium. The under-sodium viewing technique by using an ultrasonic wave should be applied far the visual inspection of reactor internals. In this study, an ultrasonic waveguide sensor with a strip plate has been developed for an application to the under-sodium viewing technique. The Lamb wave propagation of a waveguide sensor has been analyzed and the zero-order antisymmetric $A_0$ plate wave was selected as the application mode of the sensor. The $A_0$ plate wave can be propagated in the dispersive low frequency range by using a liquid wedge clamped to the waveguide. A new technique is presented which is capable of steering the radiation beam angle of a waveguide sensor without a mechanical movement of the sensor assembly The steering function of the ultrasonic radiation beam can be achieved by a frequency tuning method of the excitation pulse in the dispersive range of the $A_0$ mode. The technique provides an opportunity to overcome the scanning limitation of a waveguide sensor. The beam steering function has been evaluated by an experimental verification. The ultrasonic C-scanning experiments are performed in water and the feasibility of the ultrasonic waveguide sensor has been verified.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.693-697
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• 2007

The SSB modem performs the modulation process which converts the digital voltage level to the audible frequency band signal and the demodulation process which converts reversely the audible frequency signal to the digital voltage level. The modulator and the demodulator are implemented with a single DSP chip. Because of the SSB specific character, the distortion occurs when the frequency is changed. This distortion has no effect on voice communication, but it has an significant effect on data communication. In other words, it is impossible to send data stream with adjacent 2 periods. Therefore, in case of using 2-tone FSK, it is needed to send at least 3 periods to transmit 1 bit. Therefore we implemented the modem using modified phase-delay shift keying to transmit 1 tone signal for high speed transmission. In the 1200[bps] mode, it generates 0, $187{\mu}s$ delay time at 1.3kHz symbol frequency, and in the 2400[bps] mode, 0, $70{\mu}s$, $130{\mu}s$, $200{\mu}s$ delay time at 1.5kHz symbol frequency. Finally, in the maximum 3600[bps] mode, it generates 0, $100{\mu}s$, $160{\mu}s$, $250{\mu}s$ delay time at 2.0kHz symbol frequency. The measured results of the implemented SSB modem shows a good transfer functional characteristic by spectrum analyzer, almost same bandwidth in pass band and 20dB higher SNR comparing the German PACTOR and American CLOVER and in the experimental transmitting test, we verified the transmitted data is received correctly in platform.

• Journal of Broadcast Engineering
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• v.25 no.5
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• pp.698-708
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• 2020

VVC (Versatile Video Coding), which has been developing as a next generation video coding standard. Compared to HEVC (High Efficiency Video Coding), VVC is improved by about 34% in RA (Random Access) configuration and about 30% in LDB (Low-Delay B) configuration by adopting various techniques such as recursive block partitioning structure and GPM (Geometric Partitioning Mode). But the encoding complexity is increased by about 10x and 7x, respectively. In this paper, we propose a fast decision method of GPM mode and block partitioning using directionality of block to reduce encoding complexity of VVC. The proposed method is to apply the Hough transform to the current block to identify the directionality of the block, thereby determining the GPM mode and the specific block partitioning method to be skipped in the rate-distortion cost search process. As a result, compared to VTM8.0, the proposed method reduces about 31.01% and 29.84% encoding complexity for RA and LDB configuration with 2.48% and 2.69% BD-rate loss, respectively.

• Journal of Broadcast Engineering
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• v.22 no.1
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• pp.28-41
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• 2017

In this paper, the fast encoding algorithm in High Efficiency Video Coding (HEVC) encoder was studied. For the encoding efficiency, the current HEVC reference software is divided the input image into Coding Tree Unit (CTU). then, it should be re-divided into CU up to maximum depth in form of quad-tree for RDO (Rate-Distortion Optimization) in encoding precess. But, it is one of the reason why complexity is high in the encoding precess. In this paper, to reduce the high complexity in the encoding process, it proposed the method by determining the maximum depth of the CU using a hierarchical clustering at the pre-processing. The hierarchical clustering results represented an average combination of motion vectors (MV) on neighboring blocks. Experimental results showed that the proposed method could achieve an average of 16% time saving with minimal BD-rate loss at 1080p video resolution. When combined the previous fast algorithm, the proposed method could achieve an average 45.13% time saving with 1.84% BD-rate loss.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.