• Journal of Broadcast Engineering
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• v.19 no.4
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• pp.491-501
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• 2014

Recently, the need for disaster-preventing broadcast has increased gradually to cope with natural disaster like earthquake and tsunami causing enormous losses of both life and property. In disaster-preventing broadcast system, the wake-up signal is used to alert user terminal and switch the current state of channel to the emergency channel, which is for the fast and efficient delivery of emergency information. In this paper, we propose the detection method of wake-up signal for disaster-preventing broadcast systems. The wake-up signals for disaster-preventing broadcast should have a good auto-correlation property in low power and narrow-band conditions that does not affect the existing digital television (DTV) system. The suitability of the m-sequence and complementary code (CC) is analyzed for wake-up signals according to signal to noise ratio. A wake-up signal is proposed by combining the direct sequence spread spectrum (DSSS) technique and pseudo noise (PN) sequences such as Barker and Walsh-Hadamard codes. By using the proposed method, a higher detecting performance can be achieved by the spreading gain compared to the single long m-sequence and the Golay code.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.144-151
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• 2022

In this paper, a 1.5V 256kb eFlash memory IP with low area DC-DC converter is designed for battery application. Therefore, in this paper, 5V NMOS precharging transistor is used instead of cross-coupled 5V NMOS transistor, which is a circuit that precharges the voltage of the pumping node to VIN voltage in the unit charge pump circuit for the design of a low-area DC-DC converter. A 5V cross-coupled PMOS transistor is used as a transistor that transfers the boosted voltage to the VOUT node. In addition, the gate node of the 5V NMOS precharging transistor is made to swing between VIN voltage and VIN+VDD voltage using a boost-clock generator. Furthermore, to swing the clock signal, which is one node of the pumping capacitor, to full VDD during a small ring oscillation period in the multi-stage charge pump circuit, a local inverter is added to each unit charge pump circuit. And when exiting from erase mode and program mode and staying at stand-by state, HV NMOS transistor is used to precharge to VDD voltage instead of using a circuit that precharges the boosted voltage to VDD voltage. Since the proposed circuit is applied to the DC-DC converter circuit, the layout area of the 256kb eFLASH memory IP is reduced by about 6.5% compared to the case of using the conventional DC-DC converter circuit.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.3
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• pp.89-95
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• 2009

H.264/AVC is the state-of-the-art video compression standard which achieves high coding efficiency compared with the previous standards. H.264/AVC adopts zig-zag scanning in order to encode quantized transform coefficients in a block. However, its performance is not satisfactory because all blocks are scanned in the fixed order without considering the characteristics of blocks. This paper presents an adaptive coefficient scanning method for improving inter coding efficiency in H.264/AVC. In the proposed method, the coefficient scanning order for each prediction mode is adaptively controlled based on the information of previously-coded blocks. The experimental results show that the proposed coefficient scanning method improves the coding efficiency about 2.29% for high-quality HD sequences.

• 전자공학회논문지 IE
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• v.47 no.2
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• pp.13-20
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• 2010

This paper describes a current mode PWM DC-DC converter IC for battery charger and supply power converter for portable electronic devices. The maximum supply voltage of IC is 40[V] and 2.8[V]~330[V] DC input power is converted to higher or programmed DC voltage according to external resistor ratio or wire winding ratio of transformer. The maximum supply output current is 3[A] over and voltage error of output node is within 3[%]. The whole circuit needed current mode PWM DC-DC converter circuit is designed. The package dimensions and number of external parts are minimized in order to get a smaller hardware size. The power consumption is smaller then 1[mW] at stand by period with supply voltage of 3.6[V] and maximum energy conversion efficiency is about 86[%]. This device has been designed in a 0.6[um] double poly, double metal 40[V] CMOS process and whole chip size is 2100*2000 [um2].

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.2
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• pp.110-118
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• 2008

The regulated peak power tracking (RPPT) systems such as the series structure and the parallel structure are commonly used in the satellite space power system. However, this structure processes the solar array power to the load through two regulators during one orbit cycle, which reduces the energy transfer efficiency. The series-parallel structure for the RPPT system can improve the power conversion efficiency, but an additional regulator increases the cost, size and weight of the system. In this paper, a simplified series-parallel space power system that consists of two regulators is proposed. The proposed system has the similar energy transfer efficiency with the series-parallel structure by adding one switch to the series structure, which reduces the cost, size and the weight. The large signal stability analyses is provided to understand the four main modes of system operation. In order to compare the energy efficiency with a series structure, the simulation is performed. The experimental verifications are performed using a prototype hardware with TMS320F2812 DSP and 200W solar arrays.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.11
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• pp.937-946
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• 2014

This paper presents system identification of a single tilt wing UAV. A Modified Equation Error Method(MEEM) and Extended Kalman Filter(EKF) are used for the identification of a single tilt wing UAV system in frequency-domain and time-domain, respectively. Simulated flight data is obtained from CNUX-3's vertical mode linear simulation with realistic sensor noise. System identification performance is analyzed with respect to a variety of design parameters of the MEEM. Also, High accuracy Fourier Transform(HFT) is applied to enhance the performance of MEEM. The results of the MEEM is compared with those of the EKF. Design parameters of the MEEM and initial conditions of the EKF are decided from optimization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.1-9
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• 2010

In this paper, the novel architecture of Intra-prediction & DCTQ hardware, which can process for the Full HD image($1980{\times}1088$@30fps) in realtime, is proposed. The cycle optimization method for the overall cycle of prediction, transform, scaling, descaling, and reconstruction is proposed. To reduce the cycle in the $4{\times}4$ prediction, the quantization process is performed during the prediction cycle and pre-selection of 2 modes among the 9 modes is performed to reduce the hardware area. To reduce the hardware of $16{\times}16$ and $8{\times}8$ prediction, the sharing logic between 2 prediction is utilized. The proposed architecture can process the 30frame/sec of full HD image in 108 MHz clock and operate 425 cycle for one macroblock.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.275-282
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• 2004

In this paper, a transcoding method that transforms MPEG-4 video bitstream coded in 30 Hz frame rate into H.264 video bitstream of 15 Hz frame rate is proposed. The block modes and motion vectors in MPEG-4 is utilized in H.264 for block mode conversion and motion vector (MV) interpolation methods. The proposed three types of MV interpolation method can be used without performing full motion estimation in H.264. The proposed transcoder reduces computation amount for full motion estimation in H.264 and provides good quality of H.264 video at low bitrates. In experimental results, the proposed methods achieves 3.2-4 times improvement in computational complexity compared to the cascaded pixel-domain transcoding, while the PSNR (peak signal to noise ratio) is degraded with 0.2-0.9dB depending on video sizes.

• Journal of Broadcast Engineering
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• v.20 no.6
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• pp.862-870
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• 2015

The RDO (Rate Distortion Optimization) process of HEVC results in good coding efficiency, but relatively requires much encoding time. In order to reduce the encoding time of RDO process, this paper proposes a method of fast intra prediction mode decision using DCT coefficients distributions and the existence of DCT coefficients. The proposed fast Intra coding sets the number of intra prediction mode candidates to three(3) from the RMD (Rough Mode Decision) process in HM16.0 reference SW and reduces the number of candidates one more time by investigating DCT coefficients distribution. After that, if there exists a quantized DCT block having all zero coefficient values for a specific candidate before the RDO process, the candidate is chosen without the RDO process. The proposed method reduces the encoder complexity on average 46%, while the coding efficiency is 2.1% decreased compared with the HEVC encoder.

• Journal of the Earthquake Engineering Society of Korea
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• v.5 no.6
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• pp.55-64
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• 2001

Industrial machines are sometimes exposed to the danger of earthquake. In the design of a mechanical system, this factor should be accounted for from the viewpoint of reliability to analyze a complex nonlinear structure system under random excitation is proposed. First, the actual random excitation, such as earthquake, is approximated to the corresponding Gaussian process for the statistical analysis. The modal equations of overall system are expanded sequentially. Then, the perturbed equations are synthesized into the overall system and solved in probabilistic way. Several statistical properties of a random process that are of interest in random vibration are evaluated in each substructure. Comparing with the results of the numerical simulation proved the efficiency of the proposed method.