• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.5
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• pp.387-396
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• 2009

The life and performance of lithium battery are greatly influenced by the formation process which is essential in the process of manufacture. Charge/discharge system for the lithium battery are required for the formation process. To simulate such a system in a conventional method takes very long time and requires huge memory space to save data files. So the simulation may be impossible with a general-purpose PC. In this paper, the lithium battery is modelled to a resistor-capacitor serial circuit and the lithium battery charge/discharge system is analyzed and simulated by using state space averaging method. As a result, the simulation time is reduced dramatically and the simulation of the lithium battery charge/discharge system becomes possible on a general-purpose PC within 3 hours. Also, both the charge/discharge characteristics and the time required to charge/discharge of the lithium battery charge/discharge system can be observed. To verify the propriety of resistor-capacitor serial circuit modeling method for lithium battery and the validity of the analysis and simulation based on state space averaging, the lithium battery charge/discharge system is composed and experimentations are carried out.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2005.11a
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• pp.171-174
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• 2005

본 논문에서는 인가의 인지학적인 두뇌 원리인 대뇌피질과 해마 신경망을 공학적으로 모델링하여 얼굴 영상의 특징 벡터들을 고속 학습하고, 각 영상의 최적의 특징을 구성할 수 있는 해마 학습 알고리즘(Hippocampal Learning Algorithm)을 개발하여 RFID를 이용한 생체인식 시스템을 제안한다. 입력되는 얼굴 영상 데이터들은 NMF(Non-negative Matrix Factorization)를 이용하여 특징이 구성되고, 이러한 특징들은 해마의 치아 이랑 영역에서 호감도 조정에 따라서 반응 패턴으로 이진화 되고, CA3 영역에서 자기 연상 메모리 단계를 거쳐 노이즈를 제거한다. CA3의 정보를 받는 CA1영역에서는 단층 신경망에 의해 단기기억과 장기기억으로 나누어서 저장되고 해당 특징의 누적 개수가 문턱치(threshold)를 만족하면 장기 기억 장소로 저장시키도록 한다. 위와 같은 개념을 바탕으로 구현되는 RFID 생체인식 시스템은 특징의 분별력과 학습속도면에서 우수한 성능을 보일 수 있다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.2
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• pp.116-125
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• 2006

We have presented a nanoelectromechanical (NEM) model based on atomistic simulations. Our models were applied to a NEM device as called a nanotube random access memory (NRAM) operated by an atomistic capacitive model including a tunneling current model. We have performed both static and dynamic analyses of a NRAM device. The turn-on voltage obtained from molecular dynamics simulations was less than the half of the turn-on voltage obtained from the static simulation. Since the suspended carbon nanotube (CNT) oscillated with the amplitude for the oscillation center under an externally applied force, the quantity of the CNT-gold interaction in the static analysis was different from that in the dynamic analysis. When the gate bias was applied, the oscillation centers obtained from the static analysis were different from those obtained from the dynamics analysis. Therefore, for the range of the potential difference that the CNT-gold interaction effects in the static analysis were negligible, the vibrations of the CNT in the dynamics analysis significantly affected the CNT-gold interaction energy and the turn-on voltage. The turn-on voltage and the tunneling resistance obtained from our tunneling current model were in good agreement with previous experimental and theoretical works.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.12
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• pp.1124-1132
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• 2011

This paper deals with smooth path generation using B-spline for fixed-wing unmanned aerial vehicles manuevering in 2D environment. Hexagonal cell representation is employed to model the 2D environment, which features increased connectivity among cells over square cell representation. Subsequently, hexagonal cell representation enables smoother path generation based on a discrete sequence of path from the path planner. In addition, we present an on-line path smoothing algorithm incorporating B-spline path templates. The path templates are computed off-line by taking into account all possible path sequences within finite horizon. During on-line implementation, the B-spline curves from the templates are stitched together repeatedly to come up with a reference trajectory for UAVs. This method is an effective way of generating smooth path with reduced on-line computation requirement, hence it can be implemented on a small low-cost autopilot that has limited computational resources.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.5
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• pp.105-111
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• 2010

In this paper the elasticity of fault-detection algorithm based on fuzzy logic is proposed through lots of experiments, justifying its validity. The four mathematical morpholgical operators was defined to detect the cracks. The cracks was detected via center of area method with ${\lambda}$-fuzzy measure of fuzzy sets. However generally favorable, the result owes to how adequate the lighting device is designed in case of the so far fine crack of pieces. In an attempt to improve the response of the system, It is designed to minimize the use of memory via LookUp table in software.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.97-104
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• 2004

This paper proposes an efficient VLSI architecture of 9-7/5-3 Lifting DWT filters that is used by lossy or lossless compression of JPEG2000. The proposed architecture uses only internal line memories to compute Lifting-DWT operations and its PE(Processing Element) has critical path with 1 multiplier and 1 adder. To reduce the number of PE, we make the vertical filter that is responsible for the column operations of the first level perform both the row and column operations of the second and following levels. As a result, the architecture has smaller hardware cost compared to that of other architectures. It was modeled in RTL level using VHDL and implemented on Altera APEX 20K FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6C
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• pp.442-449
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• 2005

In this paper, we introduce three kinds of simplified high-speed decoding algorithms for turbo product decoder. First, A parallel decoder structure, the row and column decoders operate in parallel, is proposed. Second, HAD(Hard Decision Aided) algorithm is used for early-stopping algorithm. Lastly, P-Parallel TPC decoder is a parallel decoding scheme, processing P rows and P columns in parallel instead of decoding one by one as that in the original scheme.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.3
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• pp.22-22
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• 2001

정보량이 많은 고화질의 동영상을 실시간으로 전송하기 위하여 압축 알고리즘을 필수적으로 사용하고 있으며, 시간적 중복성을 제거하는 동영상의 압축방법은 움직임 추정 알고리즘을 사용한다. 본 연구에서 설계하고자 하는 움직임 추정기는 블록정합 알고리즘이며, MPEG 부호기에서 사용되는 DCT 연산 결과인 DC 값을 이용하여 화면의 밝기를 판단한다. 움직임 추정기는 휘도 신호 8비트 모두를 사용하지 않고, 화면 밝기에 따른 비트 플레인(bit plane)에서 3비트만 선택하는 비교선택기를 이용한다. 본 연구에서 제안한 비교 선택기는 I-Picture만을 계산한다. I-Picture에 의해 계산된 선택 비트는 I, P와 B Picture의 움직임 추정 연산에 사용함으로서 움직임 추정기의 크기를 줄일 수 있는 구조를 제안하였다. 제안된 움직임 추정기의 고찰을 위하여 실험에 사용된 표준 동영상의 해상도는 352×288이며, DCT 연산의 처리 블록은 8×8이며, 탐색 영역은 23×23이다. 제안된 알고리즘은 C언어로 모델링하였으며, 기존 완전탐색방법과 PSNR을 비교한 결과 사람의 시각으로 거의 구별할 수 없는 작은 차이(0～0.83dB)가 나타남을 알 수 있었다. 본 연구에서 제안한 움직임 추정기의 하드웨어 크기는 기존 구조Ⅰ보다 38.3%, 기존 구조Ⅱ보다 30.7% 줄일 수 있었고, 메모리 크기는 기존 구조Ⅰ,Ⅱ보다 31.3% 줄일 수 있었다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.4
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• pp.331-335
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• 2004

In this paper, we modeling the oxidation, diffusion, and ion-implantation for semiconductor process simulation, and construct the integrated framework for efficient execution and continuous process simulation. For oxidation process, to predict the accurate LOCOS shape and stress distributions, stress-dependent viscous model was performed using SVP algorithm. For diffusion process, predeposition and OED simulation was performed using point defect theory. For ion implantation, Monte-Carlo method based on TRIM simulation was performed with various process conditions. For input to each unit process, we used the dialog boxes which are windows application's standards. This dialog box allows us to verify and minimize input error at input steps. Using the combination of compiler's function and windows's API function, simulation was done with small memory size.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.5
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• pp.263-272
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• 2011

The complexity of flash memory based storage systems is high due to diverse host interfaces and other design choices such as mapping granularity, flash memory controller execution models and so on. Thus, it is possible that the actual performance after implementation is not consistent with the target performance. This paper demonstrates that the performance prediction of flash memory based storage systems is possible through performance modeling that takes into account various design parameters. In the performance modeling, the FTL, which is the core element of flash memory based storage systems, is modeled as a set of (copy-on-write) logs and their interactions. Also, the flash memory controller is modeled based on the classification proposed in the design of the Ozone flash controller. In this study, the performance model has been implemented using Simulink and experimental results are presented and analyzed.