• The Journal of the Korea Contents Association
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• v.8 no.9
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• pp.27-33
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• 2008

This paper designs Shared Memory on the Dual Core system so that it operates a general System V IPC on the Linux O.S. Shared Memory is the technique that many processes can access to identical memory area. We treat Shared Memory which is SVR in a kernel step. We design a share memory facility of Linux operating system on the Dual Core System. In this paper the suggesting of share memory facility design plan in Dual Core system is enhance the performance in existing an unity processor system as a dual core practical use. We attemp a performance enhance in each CPU for each process which uses a share memory.

• Journal of IKEEE
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• v.17 no.2
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• pp.168-175
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• 2013

The delay times due to the propagating of data on PCB depend on the shape and length of interconnection lines when memory controllers and high speed memories are soldered on the PCB. The dependency on the placement and routing on the PCB requires redesign of I/O logic or reconfiguration of the memory controller after the delay time is measured if the controller is programmable. In this paper, we propose architecture of configuring logic for the delay time estimation by writing and reading test patterns while initializing the memories. The configuration logic writes test patterns to the memory and reads them by changing timing until the correct patterns are read. The timing information is stored and the configuration logic configures the memory controller at the end of initialization. The proposed method enables easy design of systems using PCB by solving the problem of the mismatching caused by the variation of placement and routing of components including memories and memory controllers. The proposed method can be applied to high speed SRAM, DRAM, and flash memory.

• Journal of Korea Multimedia Society
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• v.2 no.1
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• pp.80-88
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• 1999

In this paper, we propose a Special Memory for Graphics(SMGRA) which accelerates memory access time for graphics operations. The SMGRA has a rectangular array memory architecture which has already proposed by Whelan to process pixels in the rectangle area simultaneously, but the SMGRA should improve address decoding time and reduce the number of address pins by using address multiplexing scheme. The SMGRA has a Z-value comparator in the DRAM which is to convert read-modify-write Z buffer into single-write only operation that improves approximately 50% frame buffer access bandwidth.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.3
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• pp.147-160
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• 2010

The system virtualization shows interest in the consolidation of servers for the efficient utilization of system resources. There are many various researches to utilize a server machine more efficiently through the system virtualization technique, and improve performance of the virtualization software. These researches have studied with the activity to control the resource allocation of virtual machines dynamically focused on CPU, or to manage resources in the cross-machine using the migration. However, the researches of the memory management have been wholly lacking. In this respect, the use of memory is limited to allocate the memory statically to virtual machine in server consolidation. Unfortunately, the static allocation of the memory causes a great quantity of the idle memory and decreases the memory utilization. The underutilization of the memory makes other side effects such as the load of other system resources or the performance degradation of services in virtual machines. In this paper, we suggest the dynamic allocation of the memory in Xen to control the memory allocation of virtual machines for the utilization without the performance degradation. Using AR model for the prediction of the memory usage and ACO (Ant Colony Optimization) algorithm for optimizing the memory utilization, the system operates more virtual machines without the performance degradation of servers. Accordingly, we have obtained 1.4 times better utilization than the static allocation.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.5
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• pp.129-140
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• 2014

BIST(Built-in self test) is to detect various faults of the existing memory and BIRA(Built-in redundancy analysis) is to repair detected faults by allotting spare. Also, BISR(Built-in self repair) which integrates BIST with BIRA, can enhance the whole memory's yield. However, the previous methods were suggested for RAM and are difficult to diagnose disturbance that is NAND-type flash memory's intrinsic fault when used for the NAND-type flash memory with different characteristics from RAM's memory structure. Therefore, this paper suggests a BISD(Built-in self diagnosis) to detect disturbance occurring in the NAND-type flash memory and to diagnose the location of fault, and BISR to repair faulty blocks.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.3
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• pp.13-19
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• 2016

Spark, an in-memory big-data processing framework is popular to use for real-time processing workload. Spark can store all intermediate data in the cluster memory so that Spark can minimize I/O access. However, when the resident memory of workload is larger that the physical memory amount of the cluster, the total performance can drop dramatically. In this paper, we analyse the factors of bottleneck on PageRank Application that needs many memory through experiment, and cluster the Spark with Tachyon File System for using memory to solve the factor of bottleneck and then we improve the performance about 18%.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.1
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• pp.87-96
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• 2006

In this paper, we examine general digital evidence collection process which is according to RFC3227 document[l], and establish specific steps for memory information collection. Besides, we include memory dump process to existing digital evidence collection process, and examine privacy information through dumping real user's memory and collecting pagefile which is part of virtual memory system. Especially, we discovered sensitive data which is like password and userID that exist in the half of pagefiles. Moreover, we suggest each analysis technique and computer forensic process for memory information and virtual memory.

• Journal of Broadcast Engineering
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• v.23 no.5
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• pp.606-613
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• 2018

This study is concerned with implementing an external memory expansion device for large-scale image processing. It consists of an external memory adapter card with a PCI(Peripheral Component Interconnect) Express Gen3 x8 interface mounted on a graphics workstation for image processing and an external memory board with external DDR(Dual Data Rate) memory. The connection between the memory adapter card and the external memory board is made through the optical interface. In order to access the external memory, both Programmable I/O and DMA(Direct Memory Access) methods can be used to efficiently transmit and receive image data. We implemented the result of this study using the boards equipped with Altera Stratix V FPGA(Field Programmable Gate Array) and 40G optical transceiver and the test result shows 1.6GB/s bandwidth performance.. It can handle one channel of 4K UHD(Ultra High Density) image. We will continue our study in the future for showing bandwidth of 3GB/s or more.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.7
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• pp.789-793
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• 2010

Recently, flash memory-based non-volatile cache (NVC) is emerging as an effective solution to enhance both I/O performance and energy consumption of storage systems. To get significant performance and energy gains by NVC, it would be better to use multi-level-cell (MLC) flash memories since it can provide a large capacity of NVC with low cost. However, the number of available program/erase cycles of MLC flash memory is smaller than that of single-level-cell (SLC) flash memory limiting the lifespan of NVC. To overcome such a limitation, SLC/MLC combined flash memory is a promising solution for NVC. In this paper, we propose an effective management scheme for heterogeneous SLC and MLC regions of the combined flash memory.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.5
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• pp.1013-1022
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• 2017

Windows hibernation is a function that stores data of physical memory on a non-volatile media and then restores the memory data from the non-volatile media to the physical memory when the system is powered on. Since the hibernation file has memory data in a static state, when the attacker collects it, key information in the system's physical memory may be leaked. Because Windows does not support protection for hibernation files only, we need to protect the memory that is written to the hibernate file. In this paper, we propose a method to encrypt the physical memory data in the hibernation file to protect the memory data of the processes recorded in the hibernation file. Hibernating procedure is analyzed to encrypt the memory data at the hibernating and the encryption process for hibernation memory is implemented to operate transparently for each process. Experimental results show that the hibernation process memory encryption tool showed about 2.7 times overhead due to the crypt cost. This overhead is necessary to prevent the attacker from exposing the plaintext memory data of the process.