• Journal of Korea Multimedia Society
• /
• v.14 no.11
• /
• pp.1478-1490
• /
• 2011

Recently, multi-core processors have been drawing significant interest from the embedded systems research and industry communities due mainly to their potential for achieving high performance and fault-tolerance at low cost in such products as automobiles and cell phones. To process multimedia data, a scheduling algorithm is required to meet timing constraints of periodic tasks in the system. Though Pfair scheduling algorithm can meet all the timing constraints while achieving 100% utilization on multi-core based system theoretically, however, the algorithm incurs high scheduling overheads including frequent core migrations and system-wide synchronizations. To mitigate the problems, we propose a real-time scheduling algorithm for multi-core based system so that system-wide scheduling is performed only when it is absolutely necessary. Otherwise the proposed algorithm performs scheduling within each core independently. The experimental results by extensive simulations show that the proposed algorithm dramatically reduces the scheduling overheads up to as negligible one when the utilization is under 80%.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.14 no.3
• /
• pp.163-169
• /
• 2014

Recently, the importance of multicore processor system is growing rapidly. Multicore processors are classified either as symmetric or asymmetric. Asymmetric multicore processors consist of a high performance complex core and number of low performance simple cores, and are known to be more efficient than symmetric multicore processors. Therefore, performance impact on various configurations of asymmetric multi-core processor needs to be studied. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for different asymmetric quad-core and octa-core processors and compared to the corresponding symmetric ones.

• Proceedings of the Korean Information Science Society Conference
• /
• 2008.06b
• /
• pp.405-410
• /
• 2008

성능 / 에너지를 강조하는 현재의 멀티코어 추세에서 임베디드 시스템에 사용되는 대부분의 프로세서들은 단일 프로세서와 메모리를 버스 형태로 연결하여 구현하였다. 하지만 칩 내부의 프로세서 코어 수가 증가 하게 되면, 기존 버스 형태의 구조는 제한된 대역폭으로 인하여 확장성이 제약된다. 본 논문에서는 멀티코어 프로세서에서 사용 가능한 기존 연결 망 구조들을 분석하고, 기존 계층적 링 구조에서의 지연 시간 문제를 극복하여 성능을 개선할 수 있는 새로운 이중 광역 계층 링 구조를 제안한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.10a
• /
• pp.321-324
• /
• 2010

There have been lots of researches on a multi-core processor. The enhancement has been performed through parallelization method. Multi-core architecture in the mobile environment has emerged. But, there is a limit to a mobile CPU's performance. GP-GPU(General-Purpose computing on Graphics Processing Units) can improve performance without adding other dedicated hardware. This paper presents the implementation of Inverse Quantization, Inverse DCT and Color Space Conversion module in H.264/AVC decoder using Multi-Core GP-GPU for a mobile environments. The proposed architecture improves approximately 50% of performance when it use all the features.

• The KIPS Transactions:PartA
• /
• v.16A no.2
• /
• pp.113-124
• /
• 2009

With increasing multicore system, much effort has been put on the performance improvement of its application. Because multicore system has multiple processing devices in one system, its processing power increases compared to the single core system. However in many cases the advantages of multicore can not be exploited fully because the existing software and hardware were designed to be suitable for single core. When the existing software runs on multicore, its performance improvement is limited by the bottleneck of sharing resources and the inefficient use of cache memory on multicore. Therefore, according as the number of core increases, it doesn't show performance improvement and shows performance drop in the worst case. In this paper we propose a method of performance improvement of multicore system by applying Flow-Level Parallelism to the existing TCP/IP network application and operating system. The proposed method sets up the execution environment so that each core unit operates independently as much as possible in network application, TCP/IP stack on operating system, device driver, and network interface. Moreover it distributes network traffics to each core unit through L2 switch. The proposed method allows to minimize the sharing of application data, data structure, socket, device driver, and network interface between each core. Also it allows to minimize the competition among cores to take resources and increase the hit ratio of cache. We implemented the proposed methods with 8 core system and performed experiment. Experimental results show that network access speed and bandwidth increase linearly according to the number of core.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.37 no.5B
• /
• pp.348-356
• /
• 2012

The application traffic analysis is getting more and more challenging due to the huge amount of traffic from high-speed network link and variety of applications running on wired and wireless Internet devices. Multi-level combination of various analysis methods is desired to achieve high completeness and accuracy of analysis results for a real-time analysis system, while requires much of processing burden on the contrary. This paper proposes a novel architecture for a real-time traffic analysis system which improves the processing performance on multi-core CPU environment. The main contribution of the proposed architecture is an efficient parallel processing mechanism with multiple threads of various analysis methods. The feasibility of the proposed architecture was proved by implementing and deploying it on our campus network.

• Journal of the Korea Society of Computer and Information
• /
• v.16 no.6
• /
• pp.11-20
• /
• 2011

In this paper, we propose an optimal scheduling scheme that minimizes the energy consumption of a real-time video task on the multi-core platform supporting dynamic voltage and frequency scaling. Exploiting parallel execution on multiple cores for less energy consumption, the propose scheme allocates an appropriate number of cores to the task execution, turns off the power of unused cores, and assigns the lowest clock frequency meeting the deadline. Our experiments show that the proposed scheme saves a significant amount of energy, up to 67% and 89% of energy consumed by two previous methods that execute the task on a single core and on all cores respectively.

• Proceedings of the Korean Information Science Society Conference
• /
• 2011.06b
• /
• pp.388-390
• /
• 2011

오늘날의 시스템은 프로세서 성능의 증가와 더불어 단일코어에서 멀티코어 환경으로 변화되었다. 이에 따라 자원 경쟁을 최소화하여 시스템의 성능을 향상시키기 위한 멀티코어 스케줄링 기법이 연구되고 있다. 기존의 기법에서는 메모리 지향적인 태스크들을 중점적으로 다루고 있으나, 실제 컴퓨팅환경에서는 다양한 워크로드가 존재한다. 따라서 각 태스크들의 특성을 반영한 스케줄링 기법이 필요하다. 본 논문에서는 HPC 관련 툴을 이용한 실험을 통해 프로세서, 메모리, I/O지향적인 태스크들의 특성을 파악하였다. 메모리 지향적인 태스크는 매우 높은 캐시 미스율을 가지고 있으며, I/O 지향적인 태스크는 시스템 콜을 매우 빈번히 호출 한다는 것을 실험을 통해 알 수 있었다. 이러한 태스크들의 특성을 스케줄러 설계에 적절히 반영한다면 보다 효율적인 스케줄링이 가능할 것으로 기대된다.

• Proceedings of the Korean Information Science Society Conference
• /
• 2012.06a
• /
• pp.245-247
• /
• 2012

최근 멀티코어 프로세서의 활용이 대중화되고 있다. 멀티코어 시스템에서는 소프트웨어가 동시에 여러 코어를 사용하여 동작을 수행 할 때 성능 향상 효과를 얻을 수 있다. 즉, 하나의 소프트웨어가 여러 코어를 동시에 사용할 수 있는 멀티스레드 프로그래밍 기법을 사용할 때 성능을 높일 수 있다. 이러한 환경에서 효율적인 메모리 할당은 데스크톱, 서버 및 과학 등과 같은 응용에 매우 중요하다. 하지만, 동적으로 메모리를 할당하는 것은 메모리 할당 연산과 반환 연산 및 어떤 스레드가 다른 스레드의 힙 영역에 접근하는 것을 처리하기 위한 동기화 문제로 인한 오버헤드가 발생하여 성능에 영향을 끼치는 문제가 발생하게 된다. 따라서 이와 같은 환경에서 실제로 성능에 어느 정도 영향을 끼칠 것인가를 측정할 수 있는 도구가 필요하다. 이에 멀티코어 환경에서 멀티스레드 기법을 사용하여 메모리 할당 연산이 성능에 어떠한 영향을 끼치는지를 측정 및 평가할 수 있는 시뮬레이터인 MAES(Memory Allocation Evaluation Simulator)를 설계하고 구현한다.

• Journal of the Korea Society of Computer and Information
• /
• v.19 no.9
• /
• pp.21-31
• /
• 2014

Singular value decomposition (SVD) has been widely used to identify unique features from a data set in various fields. However, a complex matrix calculation of SVD requires tremendous computation time. This paper improves the performance of a representative one-sided block Jacoby algorithm using a two-dimensional (2D) multi-core system. In addition, this paper explores an optimal multi-core system by varying the number of processing elements in the 2D multi-core system with the same 400MHz clock frequency and TSMC 28nm technology for each matrix-based one-sided block Jacoby algorithm ($128{\times}128$, $64{\times}64$, $32{\times}32$, $16{\times}16$). Moreover, this paper demonstrates the potential of the 2D multi-core system for the one-sided block Jacoby algorithm by comparing the performance of the multi-core system with a commercial high-performance graphics processing unit (GPU).