• Journal of KIISE
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• v.42 no.2
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• pp.177-182
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• 2015

The era of multi-core processors has begun since the limit of the clock speed has been reached. These days, multi-core technology is used not only in desktops, servers, and table PCs, but also in smartphones. In this architecture, there is always interference between processes, because of the sharing of system resources. To address this problem, cache partitioning is used, which can be roughly divided into two types: software and hardware cache partitioning. When it comes to dynamic cache partitioning, hardware cache partitioning is superior to software cache partitioning, because it needs no page copy. In this paper, we compare the effectiveness of hardware and software cache partitioning on the AMD Opteron 6282 SE, which is the only commodity processor providing hardware cache partitioning, to see whether this technique can be effectively deployed in dynamic environments.

• Journal of Aerospace System Engineering
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• v.13 no.5
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• pp.1-8
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• 2019

Recently, avionics has been migrating from a federated architecture to an integrated modular architecture based on a multi-core to reduce the number of systems, weight, power consumption, and platform redundancy. The volume of data which must bo provided to the pilot through the display device has increased, because an integrated single device performs multiple functions. For this reason, the volume of data processed by the graphic processor within a fixed operation period has increased. In this paper, we provide a multi-core-based rendering engine in to perform more graphics processing within a fixed operation period. We assume the proposed method uses a multi-core-based partitioning operating system using the AMP (Asymmetric Multi-Processing) architecture.

• Journal of IKEEE
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• v.19 no.3
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• pp.357-365
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• 2015

Recently, embedded systems such as aircraft and automobilie, are developed as modular architecture instead of federated architecture because of SWaP(Size, Weight and Power) issues. In addition, partition operating system that support multiple logical node based on partition concept were recently appeared. Distributed recovery block is fault tolerance design scheme that applicable to mission critical real-time system to support real-time take over via real-time synchronization between participated nodes. Because of real-time synchronization, single-core based computer is not suitable for partition based distributed recovery block design scheme. Multi-core and AMP(Asymmetric Multi-Processing) based partition architecture is required to apply distributed recovery block design scheme. In this paper, we proposed design scheme of distributed recovery block on the multi-core based supervised-AMP architecture partition operating system. This paper implements flight control simulator for avionics to check feasibility of our design scheme.

• Journal of Aerospace System Engineering
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• v.13 no.5
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• pp.57-64
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• 2019

Recently, avionics systems are being developed as integrated modular architecture applying the modular integration design of the functional unit to reduce maintenance costs and increase operating performance. Additionally, a partitioning operating system based on virtualization technology was used to process various mission control functions. In virtualization technology, the CPU processing load distribution is a key consideration. Especially, the uncertainty of the I/O processing time is a risk factor in the design of reliable avionics systems. In this paper, we examine the influence of the I/O processing method by comparing and analyzing the CPU processing load by the I/O processing method through use of case analysis and applying it to the example of spatial-temporal partitioning.

• KIISE Transactions on Computing Practices
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• v.21 no.4
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• pp.315-319
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• 2015

This paper addresses the design and implementation of an Android application for real-time precise motion control. To provide stable real-time performance, we implemented the application in two parts: Android service in the form of a daemon process, which periodically transfers a set of position commands for all motors through a real-time fieldbus, and Android UI application, which generates and delivers the set of position commands to the Android service. To support such a real-time motion control application, we use multi-core partitioning, which partitions the processor cores into a real-time partition to be used by the real-time motion control service and a non-real-time partition to be used by the Android application, and set up a shared buffer between them for communication. Our experiments show that we can obtain a motion control period of 2 ms with 99% task activation jitters less than ${\pm}55{\mu}s$ for a configuration where each of the four threads controls two motors in a group.