• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.589-592
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• 2016

The period of the previous multi-core could be helped to improve program performance, based on the development of the hardware. However, one of the core performance enhancements for this encounter limitations and become the common way of multi-core with multiple cores. Modern programming concurrency that improves the conventional method for using threads of the kernel level in order to use the multi-core come to the fore. Using modern lightweight thread concurrency programming is to optimize the benefits of multi-core. Also sharing the absence of available data that can change is a major consideration when writing concurrent code. This paper describes the key considerations when creating a discussion concurrent code, and these issues are being supported in any way in the language of one 'go' of technologies that support the modern concurrency, and even how to write better code concurrency.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.04a
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• pp.544-545
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• 2015

최근 스토리지 서버에 사용되는 코어가 싱글코어에서 점차 발전하여 멀티코어가 됨에 따라 스토리지 서버에 많은 기능들이 추가되었다. 이러한 기능들을 효과적으로 사용하기 위해서는 스토리지 서버를 효율적으로 관리하는 프로그램이 필요하다. 이에 멀티코어를 효과적으로 사용하여 스토리지 서버를 효율적으로 관리할 수 있도록 멀티쓰레드 프로그램으로 스토리지 서버 프로그램을 구현하였다. 멀티쓰레드 소프트웨어는 동시 동작으로 인해 개발하는데 어려움이 있으므로 이를 해결코자 DEVS 형식론 기반의 멀티쓰레드 소프트웨어 개발 방법을 이용하였다. DEVS 형식론 기반의 모델링과 시뮬레이션을 거치고 소프트웨어를 구현하여 개발의 어려움과 검증에 대한 부분을 해결하였다.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.31-39
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• 2013

In this paper, we propose a power-efficient scheduling scheme that stochastically minimizes the power consumption of a real-time parallel task while meeting the deadline on multicore processors. The proposed scheme applies the parallel processing that executes a task on multiple cores concurrently, and activates a part of all available cores with unused cores powered off, in order to save power consumption. It is proved that the proposed scheme minimizes the mean power consumption of a real-time parallel task with probabilistic computation amount on DVFS-enabled multicore processors with a finite set of discrete clock frequencies. Evaluation shows that the proposed scheme saves up to 81% power consumption of the previous method.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.3
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• pp.203-208
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• 2017

Recently, the importance of DRAM is very significant in multicore processors which are widely used in computers, laptops, tablet PCs, and mobile devices. To keep up with this, both industry and academia have actively studied various types of future DRAMs. Therefore, accurate DRAM model is requisite when evaluating the multicore processor performance. In this paper, a multicore processor trace-driven simulator which can couple with the cycle-accurate DRAM simulator has been developed. Using SPEC 2000 benchmarks as input, the effect of cycle-accurate DDR3 model on the multicore processor performance has been evaluated.

• The Journal of Korean Institute of Next Generation Computing
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• v.15 no.2
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• pp.39-49
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• 2019

Recently, CPU-GPU integrated heterogeneous multicore processors have been widely used for improving the performance of computing systems. Heterogeneous multicore processors integrate CPUs and GPUs on a single chip where CPUs and GPUs share the LLC(Last Level Cache). This causes a serious cache contention problem inside the processor, resulting in significant performance degradation. In this paper, we propose the partitioned LLC architecture to solve the cache contention problem in heterogeneous multicore processors. We analyze the performance impact varying the LLC size of CPUs and GPUs, respectively. According to our simulation results, the bigger the LLC size of the CPU, the CPU performance improves by up to 21%. However, the GPU shows negligible performance difference when the assigned LLC size increases. In other words, the GPU is less likely to lose the performance when the LLC size decreases. Because the performance degradation due to the LLC size reduction in GPU is much smaller than the performance improvement due to the increase of the LLC size of the CPU, the overall performance of heterogeneous multicore processors is expected to be improved by applying partitioned LLC to CPUs and GPUs. In addition, if we develop a memory management technique that can maximize the performance of each core in the future, we can greatly improve the performance of heterogeneous multicore processors.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.290-293
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• 2014

모바일 디바이스의 보급으로 사람들의 생활에 많은 변화를 가져왔으며, 이러한 변화에 따라 점차 수요에 따른 모바일 콘텐츠 시장 또한 확산 되었다. 사람들의 수요에 의해 모바일 애플리케이션은 문서작성, 게임, 사진, 은행 업무, 영화, 벨소리 뿐 아니라 HD 비디오 재생, 스트리밍 AV 서비스 등 하드웨어적 고성능을 요구하는 애플리케이션까지 등장하게 되었다. 이러한 추세에 더불어 모바일 디바이스는 멀티코어의 성능에 이르는 디바이스까지 출시 되었다. 하지만 멀티코어의 효율성은 스케쥴러가 코어에 작업을 할당하는 방법에 따라 달라진다. 이종 멀티 코어 플랫폼에서 애플리케이션의 실행 시간은 실행되는 코어에 의존한다. 본 논문에서는 프로파일에 의해 각 태스크의 실행 시간을 분석하여 태스크 스케쥴링 기법을 제안한다.

• Journal of Satellite, Information and Communications
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• v.9 no.4
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• pp.73-76
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• 2014

With the increasing popularity of multi-core processors, they have been adopted even in embedded systems. Under this circumstance many multimedia applications can be parallelized on multi-core platforms because they usually require heavy computations and extensive memory accesses. This paper proposes an efficient thread-level parallel implementation for color space conversion on multi-core CPU. Thread-level parallelism has been becoming very useful parallel processing paradigm especially on shared memory computing systems. In this work, it is exploited by allocating different input pixels to each thread for concurrent loop executions. For the performance evaluation, this paper evaluate the performace improvements for color conversion on multi-core processors based on the processing speed comparison between its serial implementation and parallel ones. The results shows that thread-level parallel implementations show the overall similar ratios of performance improvements regardless of different multi-cores.

• Proceedings of the Korean Society of Computer Information Conference
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• 2017.07a
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• pp.1-2
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• 2017

본 논문에서는 지휘무장통제체계(이하 CFCS) 소프트웨어의 성능 향상 기법으로 고성능 컴퓨팅(이하 HPC) 시스템 활용 기법을 제안한다. 이 기법으로 본 논문에서는 HPC 분야인 멀티코어 프로세서를 활용하는 방법을 제안한다. 복잡한 반복연산을 하는 작업이 많은 CFCS의 특정 SW모듈에 대해 멀티코어 프로세싱 아키텍처를 이용한 병렬처리를 적용하여 기존 순차처리 대비 작업실행시간을 단축함으로써 작업 응답시간을 상당히 줄일 수 있다. 본 논문에서는 CFCS 시험 환경의 일부 특정 SW모듈 상에서 기존의 순차처리 방식으로 수행한 연산 결과와 다중 처리 프로그래밍 API인 OpenMP를 적용하여 수행한 연산 결과를 비교하여 CFCS에서의 멀티코어 프로세싱이 체계 전반의 성능 향상 면에서 효율적으로 사용될 수 있음을 보인다.

• Journal of the Korea Society of Computer and Information
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• v.19 no.9
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• pp.21-31
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• 2014

Singular value decomposition (SVD) has been widely used to identify unique features from a data set in various fields. However, a complex matrix calculation of SVD requires tremendous computation time. This paper improves the performance of a representative one-sided block Jacoby algorithm using a two-dimensional (2D) multi-core system. In addition, this paper explores an optimal multi-core system by varying the number of processing elements in the 2D multi-core system with the same 400MHz clock frequency and TSMC 28nm technology for each matrix-based one-sided block Jacoby algorithm ($128{\times}128$, $64{\times}64$, $32{\times}32$, $16{\times}16$). Moreover, this paper demonstrates the potential of the 2D multi-core system for the one-sided block Jacoby algorithm by comparing the performance of the multi-core system with a commercial high-performance graphics processing unit (GPU).

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.25-33
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• 2014

This paper proposes a power-efficient scheduling scheme that stochastically minimizes the power consumption of real-time tasks while meeting their deadlines on multicore processors. In the proposed scheme, uncertain computation amounts of given tasks are translated into probabilistic computation amounts based on their past completion amounts, and the mean power consumption of the translated probabilistic computation amounts is minimized with a finite set of discrete clock frequencies. Also, when system load is low, the proposed scheme activates a part of all available cores with unused cores powered off, considering the leakage power consumption of cores. Evaluation shows that the scheme saves up to 69% power consumption of the previous method.