• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.3
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• pp.339-349
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• 2017

This paper proposes a four-stage algorithm for detecting lanes on a driving car. In the first stage, it extracts region of interests in an image. In the second stage, it employs a median filter to remove noise. In the third stage, a binary algorithm is used to classify two classes of backgrond and foreground of an input image. Finally, an image erosion algorithm is utilized to obtain clear lanes by removing noises and edges remained after the binary process. However, the proposed lane detection algorithm requires high computational time. To address this issue, this paper presents a parallel implementation of a real-time line detection algorithm on a multi-core architecture. In addition, we implement and simulate 8 different processing element (PE) architectures to select an optimal PE architecture for the target application. Experimental results indicate that 40×40 PE architecture show the best performance, energy efficiency and area efficiency.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.3
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• pp.66-77
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• 2002

This paper deals with an implementation of the navigation parameter extraction technique using the TMS320C80 multimedia video processor (MVP). Especially, this Paper focuses on the relative position estimation algorithm which plays an important role in real-time operation of the overall system. Based on the relative position estimation algorithm using the images obtained at two locations, we develop a fast algorithm that can reduce large amount of computation time and fit into fixed-point processors. Then, the algorithm is reconfigured for parallel processing using the 4 parallel processors in the MVP. As a result, we shall demonstrate that the navigation parameter extraction system employing the MVP can operate at full-frame rate, satisfying real-time requirement of the overall system.

• Journal of IKEEE
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• v.15 no.4
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• pp.345-353
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• 2011

Recently portable mobile devices such as smart-phones and notebooks have rapidly increasing demands. Those devices consume more power because they are expected to offer more complex functionality including multimedia features. For these reasons engineering efforts are changing to focus on maximizing energy efficiency within a limited battery capacity instead of increasing computational performance. In this paper, we propose a battery management system using event driven programming technique on a embedded processor. We also show that the proposed system satisfies SBS (Smart Battery Specification) v1.1. The proposed system maintains minimum code size and memory size comparing to those of RTOSs. The proposed system can be also easily incorporated in the conventional RTOSs as a form of firmware.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8A
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• pp.820-829
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• 2006

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.592-607
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• 2006

This paper proposes a technique to select processors and hardware IPs and to map the tasks into the selected processing elements, aming to achieve high performance with minimal system cost when multitask applications with real-time constraints are run on a multicore SoC. Such technique is called to 'Hardware-Software Cosynthesis Technique'. A cosynthesis technique was already presented in our early work [1] where we divide the complex cosynthesis problem into three subproblems and conquer each subproblem separately: selection of appropriate processing components, mapping and scheduling of function blocks to the selected processing component, and schedulability analysis. Despite good features, our previous technique has a serious limitation that a task monopolizes the entire system resource to get the minimum schedule length. But in general we may obtain higher performance in multitask multicore system if independent multiple tasks are running concurrently on different processor cores. In this paper, we present two mapping techniques, task mapping avoidance technique(TMA) and task mapping pinning technique(TMP), which are applicable for general cases with diverse operating policies in a multicore environment. We could obtain significant performance improvement for a multimedia real-time application, multi-channel Digital Video Recorder system and for randomly generated multitask graphs obtained from the related works.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.148-155
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• 2006

Portable embedded systems which mainly handle multimedia applications involve the problem that frequent accesses to fetch data from memory make running time increased. To cope with the problem, embedded processors have adopted data prefetching schemes. From a power point of view, which is a main performance indicator of embedded systems, this paper analyzed to investigate how data prefetching schemes influence on system's performance. To solve the problem, we proposed a power-consumption analysis model of a memory system with data prefetching scheme and measured the power dissipated during running application programs. As a result data prefetching schemes have application program's running time reduced but have system's power increased. Also we proposed a performance analysis model considering execution time and power consumption for embedded system with data prefetching schemes.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.61-64
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• 2004

최근 PDA(Personal Digital Assistants)와 같은 휴대형 단말기들은 다양한 멀티미디어 기술과 무선 인터넷 기술의 영향으로 정보단말기로서 각광을 받고 있다. 그러나 현재의 단말기는 프로세서와 메모리의 한계로 인하여 원활한 음성인식 시스템을 구축하기에는 한계가 있다. 이를 보완하는 방법으로 본 논문에서는 Client/server로 분리된 음성 인식 시스템을 구축하였다. 구축한 시스템은 무선 네트워크 환경을 이용하여 PDA(Personal Digital Assistants)에서 음성 파일 또는 특징 파라미터를 Serve 측으로 전송하여 Server측에서 음성 인식을 수행한 후 그 결과를 모바일 단말기로 되돌려 주는 시스템이다. 구성된 시스템을 평가하기 위해서는 국어 공학센터의 음성 DB(KLE 452DB)를 이용하여 음향 모델을 생성한 후 다양한 환경(연구실, 복도, 주차장 도서관 로비)에서 발성한 후 이를 교내 무선 인터넷망(Nespot)을 통하여 송신하여 실시간 인식하였다. 실험 결과, 각각 $84.04\%\;72.28\%\;69.47\%\;67.61\%$의 평균 인식률을 얻을 수 있었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.410-415
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• 2002

This paper describes the implementation of a SoC(System-on-a-Chip) and an ISDN communication terminal by the SoC in ISDN network. The SoC has been developed with the functions of 32-bit ARM7TDMI RISC core processor, network connection with S/T interface, TDM--bus interface and voice codec, user interface. And we also review the developed software structure and the ISDN service protocol procedures which are working on the SoC. And finally this paper describers a structure of an ISDN terminal equipment using the implemented SoC and terminal software.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.19-25
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• 2006

The fast processing ability of an RTOS (Real Time Operating System) is one of important factors in determining the performance of embedded systems. With the development of multimedia and telecommunication technology, the higher level of performance environments is required. Moreover there is some difficulty in improving the performance of an RTOS which is based on a microprocessor. In this paper, we propose a hardware architecture to implement some functions of uC/OS-II as a target RTOS for the purpose of its performance improvement. The proposed architecture for uC/OS-II is implemented and analyzed with the performance comparison.

• Journal of Broadcast Engineering
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• v.20 no.6
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• pp.963-966
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• 2015

This paper introduces a programmable multi-format video decoder(MFD) to support HEVC(High Efficiency Video Coding) standard and for other video coding standards. The goal of the proposed MFD is the high-end FHD(Full High Definition) video decoder needed for a DTV(Digital Tele-Vision) SoC(System on Chip). The proposed platform consists of a hybrid architecture that is comprised of reconfigurable processors and flexible hardware accelerators to support the massive computational load and various kinds of video coding standards. The experimental results show that the proposed architecture is operating at a 300MHz clock that is capable of decoding HEVC bit-stream of FHD 30 frames per second.