• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.1
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• pp.47-58
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• 2018

The heterogeneous cellular network (HCN) is most significant as a key technology for future fifth generation (5G) wireless networks. The heterogeneous network considered consists of randomly macrocell base stations (MBSs) overlaid with femtocell base stations (BSs). The stochastic geometry has been shown to be a very powerful tool to model, analyze, and design networks with random topologies such as wireless ad hoc, sensor networks, and multi- tier cellular networks. The HCNs can be energy-efficiently designed by deploying various BSs belonging to different networks, which has drawn significant attention to one of the technologies for future 5G wireless networks. In this paper, we propose switching off/on systems enabling the BSs in the cellular networks to efficiently consume the power by introducing active/sleep modes, which is able to reduce the interference and power consumption in the MBSs and FBSs on an individual basis as well as improve the energy efficiency of the cellular networks. We formulate the minimization of the power onsumption for the MBSs and FBSs as well as an optimization problem to maximize the energy efficiency subject to throughput outage constraints, which can be solved the Karush Kuhn Tucker (KKT) conditions according to the femto tier BS density. We also formulate and compare the coverage probability and the energy efficiency in HCNs scenarios with and without coordinated multi-point (CoMP) to avoid coverage holes.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.201-208
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• 2012

In this paper, the hardware design of rate control for real-time video encoded is proposed. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. For high speed and low computational prediction, the MAD is predicted based on the coded basic unit, using spacial and temporal correlation in sequences. The rate control is designed with the hardware for fast QP decision. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. In addition, the rate control is designed with the hardware for fast QP decision. The execution cycle and gate count of the proposed architecture were reduced about 65% and 85% respectively compared with those of previous architecture. The proposed RC was implemented using Verilog HDL and synthesized with UMC $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count of the architecture is about 19.1k with 108MHz clock frequency.

• Journal of the Korea Concrete Institute
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• v.19 no.1
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• pp.39-46
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• 2007

In this study, for the establishment of the performance evaluation methods and the quality control standards of durability recovery method, the quantitative exposure data by long term exposure test under the coast and normal atmosphere is accumulated and analyzed. Investigating and evaluating the result of exposure test during 30 months of exposure age under the coastal and normal atmosphere environment, carbonation depth and chloride-ion penetration depth very little penetrated than cover depth. It seems reasonable to conclude that main cause of Corrosion of reinforcing bar are chloride-ion and macro cell from the result of corrosion area and corrosion velocity. Therefore, it is considered to be applied as the fundamental data on the performance evaluation and quality control standards of repair material and method through continuous exposure test in the future.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.765-770
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• 2012

In this paper, we proposed an effective hardware structure using DCT-based inra-prediction mode selection to reduce computational complexity caused by intra mode decision. In this hardware structure, the input block is transformed at first and then analyzed to determine its texture directional tendency. the complexity has solved by performing intra prediction in only predicted edge direction. $4{\times}4$ DCT is calculated in one cycle using Multitransform_PE and Inta_pred_PE calculates one prediction mode in two cycles. Experimental results show that the proposed Intra prediction encoding needs only 517 cycles for one macroblock encoding. This architecture improves the performance by about 17% than previous designs. For hardware implementation, the proposed intra prediction encoder is implemented using Verilog HDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis results show that the proposed architecture can run at 125MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.391-396
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• 2013

In this paper, for HEVC decoding, an SAO hardware design with less processing time and reduced area is proposed. The proposed SAO hardware architecture introduces the design processing $8{\times}8$ CU to reduce the hardware area and uses internal registers to support $64{\times}64$ CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC $0.18{\mu}m$ library, the gate area is 30.7k and the maximum frequency is 250MHz. The proposed SAO hardware architecture can process the decode of a macroblock in 64 cycles.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2A
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• pp.128-137
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• 2006

In this paper, we propose a wireless network discovery scheme which support effective device power management by employing battery efficient network scanning procedure. Multi-mode terminals need to discover other wireless systems, above all, to execute an inter-system handover in the environment of heterogeneous wireless networks. The existing methods introduced in some recent research reports have certain shortcomings, such as battery power consumption increased by frequent modem activation, or the multi-mode terminal's inability to promptly discover wireless system. We Propose a scheme in which multi-mode terminals more quickly and accurately discover other wireless systems than previous schemes, while consuming minimum power. It also proves that the scheme has better performance by comparing it with the existing schemes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.12
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• pp.1261-1266
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• 2014

Smart shipyard, all of the business of shipyard by using a mobile application, and the rapid spread of smart equipment, the overload of infrastructure due to a variety of mobile services is expected. Because macrocell and femtecell to reduce the overloading of existing infrastructure, additional core network devices have a problem, in this paper, the efficiency of resources than the communication over the existing infrastructure smart shipyard network to improve, to apply the D2D communication technology that can reduce the load on the infrastructure. The proposed routing path plan in accordance with the transfer method and the traffic type of network configuration and D2D equipment navigation and data for applying a smart shipyard. Whether to execute the function to overload traffic in the core network can send to the optimized path was confirmed by using the state transition diagram. Smart shipyard, by applying D2D communication allow efficient traffic handling than conventional communication method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.21-29
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• 2012

This paper presents optimized searching technique to improve the performance of H.264/AVC. By using the proposed forward and backward searching algorithm, redundant cycles of latency for data reordering can be removed. Furthermore, in order to reduce the total number of execution cycles of CAVLC encoder, early termination mode and two stage pipelined architecture are proposed. The experimental result shows that the proposed architecture needs only 36.0 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 57.8% than that of previous designs. The proposed CAVLC encoder was implemented using Verilog HDL and synthesized with Magnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 17K with 125Mhz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.52-60
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• 2008

The deblocking filter in the H.264/AVC video coding standard helps to reduce the blocking artifacts produced in the decoding process. But it consumes one third of the computational complexity in H.624/AVC decoder, which advocates an efficient design of a hardware accelerator for filtering. This paper proposes an architecture of deblocking filter using two filters and some registers for data reuse. Our architecture improves the throughput and minimize the number of external memory access by increasing data reuse. After initialization, two filters are able to perform filtering operation simultaneously. It takes only 96 clocks to complete filtering for one macroblock. We design and synthesis our architecture using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 200MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.55-61
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• 2000

This paper presents an efficient hardware architecture of frame memory interface in MPEG-2 video encoder. To reduce the size of memory buffers between SDRAM and the frame memory module, the number of clocks needed for each memory access is minimized with dual bank operation and burst length change. By allocating the remaining cycles not used by SDRAM access, to the random access cycle, the internal buffer size, the data bus width, and the size of the control logic can be minimized. The proposed architecture is operated with 54MHz clock and designed with the VT $I^{тм}$ 0.5 ${\mu}{\textrm}{m}$ CMOS TLM standard cell library. It is verified by comparing the test vectors generated by the c-code model with the simulation results of the synthesized circuit. The buffer area of the proposed architecture is reduced to 40 % of the existing architecture.