• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.781-783
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• 2005

ARM 프로세서는 내장형 시스템에서 가장 널리 사용되는 32비트 마이크로 프로세서 중 하나이며, Thumb 명령어 세트는 보다 작은 코드 크기를 위해 제공하는 16비트 확장 명령어 세트이다. Thumb의 약점중의 하나는 줄어든 명령어 길이 때문에 이용할 수 있는 레지스터의 개수가 반으로 줄어든다는 것인데 결과적으로 가용 레지스터의 부족으로 인해 spill 코드가 빈번하게 발생할 수 있다. 우리는 약간의 하드웨어 및 명령어 수정을 통해 뱅크(bank)로 이루어진 레지스터 파일을 제공하고자 한다. 이로 인해 컴파일러는 보다 여유 있는 레지스터를 확보하게 되어 spill 코드가 줄어들게 되므로 보다 작은 크기의 코드를 얻어낼 수 있다. 이 변화된 형태의 레지스터 파일을 운용하기 위한 효율적인 레지스터 할당기법이 요구되며, 제안하는 영역기반 레지스터 할당기법을 통해 이이 최적화된 Thumb 코드 대비 약 $5.1\%$의 코드 크기 감소효과를 볼 수 있었다.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.512-522
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• 2003

For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Typically, the size of the chip required to implement the circuit depends on both the maximum number of the LUT blocks required to implement the function of each subcircuit and the maximum number of micro-registers to store results over context switches in the same time. Therefore, many partitioning or synthesis methods try to minimize these two factors. In this paper, we present a new estimation technique to find the lower bound on the number of micro-registers which can be obtained by any synthesis methods, respectively, without performing any actual synthesis and/or design space exploration. The lower bound estimation is very important in sense that it greatly helps to evaluate the results of the previous work and even the future work. If the estimated lower bound exactly matches the actual number in the actual design result, we can say that the result is guaranteed to be optimal. In contrast, if they do not match, the following two cases are expected: we might estimate a better (more exact) lower bound or we find a new synthesis result better than those of the previous work. Our experimental results show that there are some differences between the numbers of micro-registers and our estimated lower bounds. One reason for these differences seems that our estimation tries to estimate the result with the minimum micro-registers among all the possible candidates, regardless of usage of other resources such as LUTs, while the previous work takes into account both LUTs and micro-registers. In addition, it implies that our method may have some limitation on exact estimation due to the complexity of the problem itself in sense that it is much more complicated than LUT estimation and thus needs more improvement, and/or there may exist some other synthesis results better than those of the previous work.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.12
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• pp.540-551
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• 2008

Today's microprocessor designs are not free from temperature as well as power consumption. As processor technology scales down, an on-chip circuitry increases power density, which incurs excessive temperature (hotspot) problem. To tackle thermal problems cost-effectively, Dynamic Thermal Management (DTM) has been suggested: DTM techniques have benefits of thermal reliability and cooling cost. However, they require trade-off between thermal control and performance loss. This paper proposes a dual integer register file structure to minimize the performance degradation due to DTM invocations. In on-chip thermal control, the most important functional unit is an integer register file. It is the hotspot unit because of frequent read and write data accesses. The proposed dual integer register file migrates read data accesses by adding an extra register file, thus reduces per-unit dynamic power dissipation. As a result, the proposed structure completely eliminates localized hotspots in the integer register file, resulting in much less performance degradation by average 13.35% (maximum 18%) improvement compared to the conventional DTM architecture.

• Journal of KIISE:Software and Applications
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• v.28 no.2
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• pp.201-209
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• 2001

고성능 마이크로 프로세서들은 성능 향상을 위해 ILP를 지원한다. 병렬성을 극대화시키기 위해서는 많은 성능 저해 요인들을 제거해야 한다. 최근에는 컴파일러의 역할을 증대시켜 이러한 요인들을 줄이기 위한 노력들이 활발히 진행되고 있다. 본 논문에서는 성능 저해 요인인 조건 분기 처리를 위하여 조건 실행과 레지스터 할당을 결합함으로써 메모리로의 대피를 최소화하고 병렬성을 향상시킬 수 있는 개선된 레지스터 할당 알고리즘을 제안한다. 제안한 방법을 적용하여 실험한 결과 간섭 그래프의 에지수가 4.47% 감소되었고 그 결과 요구되는 대피 변수의 수도 21.35% 감소되었다. 그리고 기존의 방법에 비해 19.38%의 성능 향상 결과를 얻었다. 결국 본 레지스터 할당 기법은 조건 실행을 통해 조건 분기 명령을 제거하여 기본 블록 내의 명령어 수를 증가시켜 병렬처리의 기회를 증진시키고 조건 분석을 통해 간섭 그래프의 불필요한 에너지를 제거시켜 보다 효율적인 레지스터 할당을 실현함으로써 제안한 방법의 타당성을 검증하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.719-722
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• 2002

임베디드 시스템을 이용하여 TCP/IP 상의 인터넷 제어시스템을 구현하였다. AT90S8535 마이크로 컨트롤러 구조 및 각종명령 레지스터 동작 원리, avr-gcc 하드웨어 프로그래밍 및 명령 레지스터의 구현원리, JAVA 애플릿 프로그래밍, 전반적인 하드웨어 기초 이론을 바탕으로 Mellow Device 1300 임베디드 시스템과 AVR90S853S 마이크로 컨트롤러 상호간의 시리얼 통신을 이용하여 원격지의 온/습도 검침 및 각종 하드웨어 디바이스의 on/off를 구현하도록 설계하였고 실시간으로 검출된 온/습도 데이터를 JAVA 애플릿을 이용하여 그래픽 챠트로 보기 쉽게 표현하였으며 A/D 변환된 온도 및 습도 데이터와 각종 H/W 디바이스 on/off 상태 데이터를 RS232 인터페이스를 이용하여 Mellow Device 1300로 송/수신하도록 구현하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9A
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• pp.763-773
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• 2003

In this paper, we present a register renaming method for conditional execution out-of-order instruction issue microprocessors. Register renaming method reduces false data dependencies (write after read(WAR) and write after write(WAW)). To implement a conditional execution out-of-order instruction issue microprocessor using register renaming, we use a register file which includes both in-order state physical registers and look-ahead state physical registers to share all logical registers. And we design an in-order state indicator, a renaming state indicator, a physical register assigning indicator, a condition prediction buffer and a reorder buffer. As we utilize the above hardwares, we can do register renaming and trace the in-order state. In this paper, we present an improved register renaming method using smaller hardware resources than conventional register renaming method. And this method eliminates an associative lookup and provides a short recovery time.

• The Magazine of the IEIE
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• v.40 no.9
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• pp.26-33
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• 2013

• Journal of Korea Multimedia Society
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• v.3 no.2
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• pp.192-200
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• 2000

8 bit and 16 bit microprocessors are widely used in the small sited control machine. The embedded microprocessors which is integrated on a single chip with the memory and I/O circuit must have simple hardware circuit and high code density. This paper proposes a 16 bit high code density EISC(Extendable Instruction Set Computer) microprocessor. SE1608 has 8 general purpose registers and 16 bit fixed length instruction set which has the short length offset and small immediate operand. By using an extend register and extend flag, the offset and immediate operand in instruction could be extended. SE1608 is implemented with 12,000 gate FPGA and all of its functions have been tested and verified at 8MHz. And the cross assembler, the cross C/C++compiler and the instruction simulator of the SE1608 have been designed and verified. This paper also proves that the code density$.$ of SE1608 shows 140% and 115% higher code density than 16 bit microprocessor H-8300 and MN10200 respectively, which is much higher than traditional microprocessors. As a consequence, the SE1608 is suitable for the embedded microprocessor since it requires less program memory to any other ones, and simple hardware circuit.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.470-476
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• 2000

This paper describes an IP design of a low-power microcontroller using an architecture level design methodology instead of a transistor level. To reduce switching capacitance, the register-toregister data transfer is adopted to frequently used register transfer micro-operations. Also, distributed buffers are proposed to reduce a input data rising edge time. To reduce power consumption without any loss of performance, pipeline processing should be used. In this paper, a 4-stage pipelined datapath being able to process CISC instructions is designed. Designed microcontroller lessens power consumption by 20%. To measure a power consumption, the SYNOPSYS EPIC powermill is used.

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.265-270
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• 2011

Even though 32-bit ISA based microprocessors are widely used more and more, 16-bit ISA based processors are still being frequently employed for embedded systems. Intel 8086, 80286, Motorola 68000, and ADChips AE32000 are the representatives of the 16-bit ISA based processors. However, due to less expressiveness of the 16-bit ISA from its narrow bit width, we need to execute more 16-bit instructions for the same implementation compared to 32-bit instructions. Because the number of executed instructions is a very important factor in performance, we have to resolve the problem by improving the expressiveness of the 16-bit ISA. In this paper, we propose a new pair register allocation algorithm to enhance an original graph-coloring based register allocation algorithm. Also, we explain about both the performance result and further research directions.