• Journal of the Korea Society of Computer and Information
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• v.11 no.3
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• pp.97-105
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• 2006

Our middle manufacturing industry need a master data management solution to adjust the changing industry environment effectively. In this paper, we development the master data management solution which has an user interface to use conveniently and has a standard data architecture for the efficient connection among various systems. Also this solution composed of the automated connection module which can make an intermediate language based on the standard data architecture and composed of the extensible production data management to improve the extensibility. This solution can provide an efficient progress information of work which was not managed by officer until now as well as can provide stable system building when we want to extend the system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.970-973
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• 2012

In cloud environment, enterprises use a number of systems which are not interconnected and save master information in a distributed way in each of them. Master information which is not managed is incorrect and discord each other so that lowers efficiency of business process and disables optimum decision making. It is necessary to do high-qualified management of master information to operate efficient and errorless business process. This paper suggests TMDM as a solution to solve heterogeneous problems occurred between interconnected master information in cloud environment and to manage business process in an efficient method. TMDM is an information storage that is suggested to solve mutual discord problems between master information using Topic Maps that considers correlation between data. Topic Maps can be connected by association between topics in order to access through a topic to all related knowledge information which is described by the topic. This also can be applied to master information between legacy systems within cloud.

• KIPS Transactions on Software and Data Engineering
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• v.3 no.11
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• pp.471-478
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• 2014

Database replication is utilized to increase credibility, availability and prevent overload of distributed databases. Two models currently exist for replication - Master/Slave and Multi-Master. Since the Multi-Master model has problems of increasing complexity and costs to interface among multiple databases for updates and inserts, the Master/Slave model is more appropriate when frequent data inserts and updates are required. However, Master/Slave model also has a problem of not having exact criteria when systems choose to connect between Master and Slave for transactions. Therefore, this research suggests a routing algorithm based on AOP (Aspect Oriented Programming) in the Master/Slave database model. The algorithm classifies applications as cross-cutting concerns based on AOP, modularizes each concern, and routes transactions among Master and Slave databases. This paper evaluates stability and performance of the suggested algorithm through integration tests based on scenarios.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.12
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• pp.2632-2640
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• 2011

In this paper, we implemented a memory controller which can accommodate data processing blocks. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Interface, Master Arbitrator, Memory Interface, Memory accelerator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.175-182
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• 2011

In this paper, we implemented a high-performence memory controller which can accommodate processing blocks(multiple masters) in SoC for video signal processing. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Selector, Mster Arbiter, Memory Signal Generator, Command Decoder, and memory Signal Generator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used. Since the designed H/W can be stably operated in 174.28MHz, it satisfies the specification of SDRAM technology.

• Journal of Internet of Things and Convergence
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• v.6 no.4
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• pp.81-87
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• 2020

This paper creates a standard node for acquiring sensor data from various industrial sensors (IoT/non-IoT) for the establishment of Smart Factory Digital Twin, and provides inter-compatible data by linking zones by group/process to secure data stability and to ensure the digital twin (Digital Twin) of Smart Factory. The process of the Zone Master platform contains interface specifications to define sensor objects and how sensor interactions between independent systems are performed and carries out individual policies for unique data exchange rules. The interface for execution control of the Zone Master Platform processor provides system management, declaration management for public-subscribe, object management for registering and communicating status information of sensor objects, ownership management for property ownership sharing, time management for data synchronization, and data distribution management for Route information on data exchange.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.369-370
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• 2007

본 논문에서는 IDLE 전송만을 수행하거나 버스접근빈도가 낮은 디폴트 마스터(Default Master)를 버스에 대한 접근빈도가 가장 높은 마스터로 재정의 하고, 버스접근빈도가 가장 높은 마스터를 찾기 위한 블록을 제작하여 추가하였다. 이 블록을 이용하여 버스에 대한 접근빈도와 데이터의 특성에 따라 디폴트 마스터를 재설정 해줄 수 있다 이로써 버스에 대한 접시간을 줄이고, 다중버스구조에서 단일버스구조와 동일한 전송이 가능하게 하여, 기존의 디폴트 마스터를 사용한 버스 구조에서 보다 효율적인 전송이 가능하다.

• Proceedings of the Korea Information Processing Society Conference
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• 2017.11a
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• pp.1109-1111
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• 2017

본 논문은 다양한 센서들과 디바이스들이 실시간으로 정보를 주고 산업 IoT 환경에서 실시간 분산 제어 역할을 하는 마스터 노드(Master Node)인 CPS시스템이 시스템장애 또는 내, 외부적인 요인으로 인해 정상적인 수행을 하지 못할 때 일시적으로 마스터 노드의 기능을 수행할 수 있는 싱크노드(Sink Node)를 선정하여 대리 마스터 노드를 결정하는 방안을 제시한다. 산업 IoT환경에서 마스터 노드의 역할로써 중요한 파라미터들을 선정한다. 이 후 상황에 따라 파라미터들의 가중치를 변경하여 우선순위 알고리즘을 통해 지속적으로 싱크 노드들의 우선순위에 대한 정보를 마스터 노드와 싱크노드들 간 공유하게 된다. 마스터 노드의 결함이 발생 시 우선순위가 높은 싱크노드가 마스터 노드의 역할을 대신 수행하여 예기치 못한 상황에도 데이터를 유지할 수 있도록 한다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.4
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• pp.71-79
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• 2011

This paper proposes a reliability enhancement of industrial real-time Ethernet using master redundancy method for NPPs(Nuclear Power Plants). In this paper, Ethernet Powerlink is investigated for distributed control systems for NPPs considering real-time and reliability performance. The proposed method can reduce a master switch-over time using PReq signal when Ethernet Powerlink master(Managing Node) failure was occurred. Using the OPNET simulation results, the performance enhancement of master switch-over time of Ethernet Powerlink is verified for NPPs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.96-102
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• 2008

The SoC bus topology is classified to single and multiple bus systems due to bus number. In single bus system, the selected only one master among the masters that try to initiate the bus transaction can execute its data transaction. On the other hand, in multiple bus system, as several buses that can be operated independently are connected with bridge, multiple data can be transferred parallel in each bus. However, In the case of data communication from one bus system to the other, data latency has remarkably increased in multiple bus. Furthermore, the performance of multiple bus can be easily different from master number, slave type and so on. In this paper, the performance of single and multiple bus architecture is compared and quantitatively analysed with the variation of master number and slave type especially a tying SDRAM, SRAM and register with TLM simulation method.