• Proceedings of the Korean Operations and Management Science Society Conference
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• 2006.05a
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• pp.110-116
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• 2006

지금까지 대부분의 리던던시 할당문제(RAP: redundancy allocation problems) 관련 연구들에서는 최상위 수준에서의 시스템 리던던시보다는 최하위 수준인 부품의 리던던시를 고려하였다. 이는 최하위 수준에서의 리던던시가 최상위 수준의 리던던시보다 효과적이라고 알려진 일반적 원리 때문이었다. 최근 한 연구에서는 동일하지 않은 예비부품을 사용하여 리던던시를 실시하는 경우 직렬구조의 시스템에서도 일반적 원리와 다른 결과가 나타날 수 있음을 보이고, 시스템을 구성하는 모든 수준에서 리던던시가 가능한 다수준 리던던시 할당문제(MRAP: multi-level RAP)를 제시하였다. 그러나 MRAP는 모든 수준에서의 리던던시를 고려하지만 단지 한 수준을 선택하여 리던던시를 할 수 있다는 가정사항을 포함하고 있다. 본 연구에서는 MRAP의 이러한 가정사항을 완화하여 시스템을 구성하는 모든 수준에서 리던던시를 위한 수준을 복수로 선택 가능한 혼합 다수준 리던던시 할당문제(MMRAP: multiple MRAP)를 제시하고 모형화하며, 문제의 해법을 위한 유전자 알고리듬(GA: genetic algorithm)을 제시한다. 제시한 GA를 활용한 몇 가지 수치실험을 통해 모형이 기존의 RAP 경우보다 효과적임을 입증한다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.11
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• pp.19-23
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• 2010

In this paper, we propose a combining scheme for partial IR based hybrid ARQ in MIMO systems. The proposed combining scheme is a symbol-level combining scheme for repeatedly transmitted systematic symbols in partial IR based hybrid ARQ. In this paper, it is shown that the proposed combining scheme can also enhance the detection performance of the parity symbols that are newly transmitted in each retransmission. Simulation results show that the proposed combining scheme significantly improves the performance of the partial IR based hybrid ARQ compared to the cases of the conventional bit-level combining scheme, especially with the ZF detection.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1877-1886
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• 2010

In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

• Journal of IKEEE
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• v.11 no.4
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• pp.129-136
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• 2007

In this paper, a simple but effective Dataline Redundancy Circuit (DRC) is proposed for a dual-port 1T-SRAM embedded in Display ICs. The DRC designed in the dual-port $320{\times}120{\times}18$-bit 1T-SRAM is verified in a 0.18-um CMOS 1T-SRAM process. In the DRC, because its control logic circuit can be implemented by a simple Shift Logic Circuit (SLC) with only an inverter and a NAND that is much simpler than the conventional, it can be placed in a pitch as narrow as a bit line pair. Moreover, an improved version of the SLC is also proposed to reduce its worst-case delay from 12.3ns to 5.9ns by 52%. By doing so, the timing overhead of the DRC can be hidden under the row cycle time because switching of the datalines can be done between the times of the word line setup and the sense amplifier setup. The area overhead of the DRC is estimated about 7.6% in this paper.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.304-305
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• 2011

정보화 사회로 진입함에 따라 전자화 된 정보의 저장 및 관리는 매우 중요한 사안으로 부각되고 있으며 모든 통신기기 및 전산시스템은 365일 가동이 보장되어야 하므로 여러 대의 전원을 병렬 운전하여 신뢰성을 높이고 용량을 증대시키는 방안이 연구되고 있다. 특히, 신뢰성이 요구되는 분야에서는 리던던시(Redundancy) 개념이 중요하게 되어 병렬 운전의 도입이 확산 되고 있다. 현재 새로운 전력 구조는 절연된 컨버터의 평균 전력량을 다운시켜 다수의 전력변환기를 병렬운전 시키는 방향으로 변하고 있으며, 이는 전력변환기의 신뢰성을 증가시키고 예비기기에 대한 부담을 감소시키는 큰 장점을 갖고 있다. 최근에는 이더넷 라이터를 이용하여 부하분담(Load Sharing) 및 핫스왑(Hot-swap)기능을 DC/DC 컨버터에 내장하고 있는 추세이다. 본 연구에서는 7[kW]급 지능형 DC 모듈전원 제어기술 개발에 초점을 두고 최적의 부하분담을 갖는 고성능 전류 제어 알고리즘을 소개하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.1977-1983
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• 1998

An algorithm-based fault tolerant scheme for the vector convolution is proposed employing the positive and negative checksum vectors that are defined in this paper based on the encoder vector. The proposed scheme is implemented on the aray processor, and then the amount of redundancy is examined thrugh the complexity analysis.

• Journal of Digital Contents Society
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• v.15 no.2
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• pp.137-145
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• 2014

In this paper, we focus on end-to-end transfer delay improvement by using erasure coding when delivering expediting message consisting of M packets in networks with high coefficient of variation of transfer time. In the scheme, M packets are divided into b groups with each having g packets. Each group is erasure coded with additional r packets and transmitted. Since the first arrived g packets among g+r packets completes the delivery of the group, the delivery time of the expediting message is reduced. For the scheme, we investigate the optimum group size and number of redundancy packets considering delivery delay reduction and additional transmission cost caused by using erasure coding. From the results of the investigation, we see that the proposed scheme is effective in networks having high variability of transfer time and would be very useful and practical especially for the case that expedited deliveries of messages are needed.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.9-16
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• 2012

In this paper, we focus on end-to-end transfer delay improvement by using network coding and propose a scheme where a message is divided into several packets which are network coded generating additional redundancy with the results that the number of transmitted packets increases. In networks with high coefficient of variation of transfer time, increased number of packets could reduce the transfer time of the message to a destination. For the proposed scheme, we investigate the optimum number of divided packets and redundancy considering transfer delay reduction and additional transmission cost caused by using network coding under the restriction of maximum transmission packet size. From the results of the investigation, we see that the proposed scheme is effective in networks having high variability of transfer time and would be very useful and practical especially for the case that expedited deliveries of messages are needed.

• Electronics and Telecommunications Trends
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• v.23 no.2 s.110
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• pp.130-141
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• 2008

본 OTH 스위치패브릭 구성방안은 OTN 망에서 다양한 클라이언트 신호를 수용하기 위한 요구사항을 기반으로 소용량에서부터 320G급 이상의 대용량까지 차세대 전송망에서 다양한 기능과 경쟁력을 갖추기 위한 OTH 스위치패브릭 구성방안을 고찰하였다. OTH 망에서 리던던시 구조 및 입출력 포트 요구조건의 설정에 따라 망 구성 및 시스템 설계를 할 수 있도록 스위치패브릭을 구성하는 방안을 제시하였다. 본 고에서는 최근 시스템 플랫폼의 세계 추세로 적용되고 있는 Advanced TCA 기반으로 백플레인 구성방법에 따라 가능한 구조를 고찰하였으며, Advanced TCA 플랫폼 및 이와 경쟁 가능한 동등 이상의 플랫폼 기반에서 적용 가능하다.

• Journal of the Korea Institute of Military Science and Technology
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• v.17 no.3
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• pp.336-341
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• 2014

When using a higher-order modulation scheme, there are variations in bit-reliability depending on the bit position in a modulation symbol. Variations of bit-reliability in the codeword block lower the decoding performance. Also, the decoding performance increases as the sum of the bit-reliabilities in the codeword block increases. This paper presents a novel hybrid automatic repeat request scheme that increases the sum of the reliabilities of the transmitted bits by lowering the modulation order, and decreases the variations of bit-reliability in the codeword block by preferentially retransmitting bits with low reliability. The proposed scheme outperforms the constellation rearrangement scheme. Furthermore, the proposed scheme also provides a good solution in cases where the size of the retransmission block is smaller than the size of the initial transmission block.