• Title/Summary/Keyword: 루프 정형

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Design of Robust QFT Controller to Damp Low Frequency Oscillations of Power System (전력계통의 저주파 진동 억제를 위한 강인하 QFT 제어기 설계)

  • 정형환;이정필;김상효;정문규;안병철
    • Journal of Advanced Marine Engineering and Technology
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    • v.25 no.4
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    • pp.833-845
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    • 2001
  • Quantitative Feedback Theory(QFT) has been used to design a robust power system stabilizer(PSS) to improve transient and dynamic stabilities of a power system. This design technique is basically accomplished in frequency domain. The most important feature of QFT is that it is able to deal with the design problem of complicated uncertain plants. A basic idea in QFT design is the translation of closed-loop frequency-domain specifications into Nichols chart domains specifying the allowable range of the nominal open-loop response and then to design a controller by using the gain-phase loop shaping technique. This paper introduces a new algorithm to compute QFT bounds more efficiently. The propose QFT design method ensures a satisfactory performance of the PSS under a wide range of power system operating conditions.

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The Synchronous Control System Design for Four Electric Cylinders (4축 전동실린더의 동기제어시스템 설계)

  • Yang, Kyong-Uk;Byun, Jung-Hwan
    • The Journal of the Korea institute of electronic communication sciences
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    • v.11 no.12
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    • pp.1209-1218
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    • 2016
  • In order to safely and speedily transport a load such as a large glass plate using four electric cylinders, the synchronous error outside the permitted range should not be continuously generated between the cylinders. In this study, a methodology of synchronous control which can be applied to synchronization of four or more cylinders is developed. The synchronous control system based on the decoupling structure is composed of a reference model, position and synchronous controllers in the respective cylinders. The reference model is used for calculating the decoupled synchronous error and control input for the each cylinder. The position controller of I-PD type is designed in order that the cylinder may follow the reference signal without overshoot and input saturation. And the synchronous controller of lead compensator is designed to achieve stable and accurate synchronization through loop shaping approach. Finally, the simulation results show that the synchronization between the four cylinders can be quickly and stably while each cylinder rod is transferred to the target point under torque disturbance.

PID Comtroller Design using Pole-Placement in the Induction Motor (유도전동기에서 극점배치기법을 이용한 PID제어기 설계)

  • Kim, Young-Chun;Cho, Moon-Taek;Song, Ho-Bin;Jung, Hyung-Keun;Lee, Sik-Chung;Maeng, Seung-Ryoul;You, Jeong-Bong
    • Proceedings of the KAIS Fall Conference
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    • 2010.11a
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    • pp.370-373
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    • 2010
  • 본 논문에서는 유도전동기와 제어기의 폐루프 극점을 원하는 위치에 배치하여 유도전동기를 위한 PID제어 동조파라미터를 얻어 유도전동기를 제어하는 방법을 제안한다. 이러한 설계방법은, 설계요건뿐만 아니라 제어기 고유의 안정도와 강인성까지 제공하므로 매우 유용하다.

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A Filtered-X LMS Algorithm by New Error Path Identification Method for Adaptive Active Noise Control (적응 능동소음제어를 위한 오차경로 인식 방법을 통한 filtered-X LMS 알고리듬)

  • 권기룡;송규익;김덕규;이건일
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.8
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    • pp.1528-1535
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    • 1994
  • In this paper, a filtered-X LMS algorithm by new error path identification method is proposed for active noise control system. The proposed algorithm identifies accurately the error path transfer function using three microphones and the control of error signal through double loop scheme with on-line. In the computer simulation using the sinusoidal and the practical duct noise, the proposed algorithm reduces noise level about 29.1dB and 10.4dB, respectively. We can observe the improvement of about 0.5dB and 2.5dB in noise level compared with that obtained using the filtered-X LMS algorithm of Eriksson model.

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The Design of Loop-shaping Two-degree-of-freedom H_{\infty} Digital Controller for Sampled-data System (샘플치 시스템의 루프정형 2자유도 H_{\infty}디지털 제어기 설계)

  • Lee, Sang-Cheol;Park, Jong-U;Jo, Do-Hyeon;Lee, Jong-Yong;Lee, Sang-Hyo
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.49 no.9
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    • pp.495-503
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    • 2000
  • In this paper we propose a design procedure of loop-shaping two-degree-of-freedom H$\infty$ digital controller for sampled-data system. We extend the continuous time loop-shaping two-degree-of-freedom H$\infty$ control problem to sampled-data system. The configuration of generalized plant is modified for sampled-data system. And then using continuous lifting we obtain the digital controller. In the final stage of loop-shaping procedure the problem of absorbing weighting functions is discussed. We summarize this study to the design procedure and illustrate the application for an inverted pendulum on the cart.

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A Novel Approach on $H_{\infty}$-LTR Controller Design ($H_{\infty}$-LTR 제어기 설계의 새로운 접근방법)

  • Lhee, Chin-Gook;Park, Jae-Sam;Ahn, Hyun-Sik;Kim, Do-Hyun
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.36S no.2
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    • pp.38-45
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    • 1999
  • In this paper, A novel approach on $H_{\infty}-LTR$ design scheme is presented. The proposed scheme provides a design toll which can trade-off the recovery error against the control input. In the first stage, Kalman filter is designed to shape the loop to satisfy the required performance specifications. The designed Kalman filter, together with the plant transfer function, is used as a target transfer function. In the second stage, sensitivity function weighted $H_{\infty}-LTR$suboptimal LTR is designed to recover the target loop transfer function. Simulation results of LQG/LTR, $H_{\infty}-LTR$are compared to demonstrate the good property of the proposed scheme.

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Design of digital clock level translator with 50% duty ratio from small sinusoidal input (작은 정현파입력의 50% Duty Ratio 디지털 클럭레벨 변환기 설계)

  • Park, Mun-Yang;Lee, Jong-Ryul;Kim, Ook;Song, Won-Chul;Kim, Kyung-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.8
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    • pp.2064-2071
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    • 1998
  • A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

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