• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2261-2268
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• 2010

The information captured by imaging devices such as CCD or CIS may contain external noises through the processes of passing signals or storing images. In this paper, we propose a Modified Sigma Filter (MSF) algorithm to reduce such noises. In experiment, we verified that our MSF algorithm showed better performance in PSNR and 1D plot of simulation results compared with Gaussian Filter (GF), Local Sigma Filter (LSF). Tested images include random Gaussian Noises.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.189-196
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• 2010

In this paper, we proposed the adaptive local sigma filter reducing noises generated by an image sensor. The small noises generated by the image sensor are amplified by increased an analog gain and an exposure time of the image sensor together with information. And the goal of this work was the system design that is reduce the these amplified noises. Edge data are extracted by Flatness Index Map algorithm. We made the threshold adaptively changeable by the luminance average in this algorithm that extracts the edge data not in high luminance, but just low luminance. The Local Sigma Filter performed only about the edge pixel that were extracted by Flatness Index Map algorithm. To verify the performance of the designed filter, we made the Window test program. The hardware was designed with HDL language. We verified the hardware performance of Local Sigma Filter system using FPGA Demonstration board and HD image sensor, $1280{\times}720$ image size and 30 frames per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.74-80
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• 2009

This paper describes a $2{\sim}6GHz$ CMOS frequency synthesizer that employs only one LC-tank voltage controlled oscillator (VCO). For wide-band operation, optimized LO signal generator is used. The LC-tank VCO oscillating in $6{\sim}8GHz$ provides the required LO frequency by dividing and mixing the VCO output clocks appropriately. The frequency synthesizer is based on a fractional-N phase locked loop (PLL) employing third-order 1-1-1 MASH type sigma-delta modulator. Implemented in a $0.18{\mu}m$ CMOS technology, the frequency synthesizer occupies the area of $0.92mm^2$ with of-chip loop filter and consumes 36mW from a 1.8V supply. The PLL is completed in less than $8{\mu}s$. The phase noise is -110dBC/Hz at 1MHz offset from the carrier.