• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.150-160
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• 1999

This paper presents a new register transfer level synthesis method to overcome the disadvantages of the previous register transfer level synthesis systems. The previous register transfer level synthesis systems first translate from a hardware description language to sequential circuits inadequately. Secondly, the systems separate registers and combinational circuits and then optimize only combinational circuits. This paper describes their disadvantages and then proposes a new method to overcome their shortcomings. This paper also shows the effectiveness of the proposed method by using the proposed method at designing the controller of a surveillance system and the 8-bit signed multiplier.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.2
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• pp.161-169
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• 2011

This paper presents a new register transfer level synthesis methodology for efficient SOC system design. The previous register transfer level synthesis systems first translate from a hardware description language to sequential circuits inadequately. Secondly, the systems separate registers and combinational circuits and then optimize only combinational circuits. This paper describes their disadvantages and then proposes a new method to overcome their shortcomings. This paper also shows the effectiveness of the proposed method by using the proposed method at designing the controller of a surveillance system.

• Journal of the Korea Society of Computer and Information
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• v.8 no.4
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• pp.111-116
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• 2003

We proposed a optimal clock period selection algorithm for low power Register Transfer Level design. The proposed algorithm use the way of maintaining the throughput by reducing supply voltage after improve the system performance in order to minimize the power consumption. In this paper, it select the low power to use pipeline in the transformation of architecture. Also, the proposed algorithm is important the clock period selection in order to maximize the resource sharing. however, it execute the optimal clock period selection algorithm. The experiment result is to set the same result AR and HAL filter on the high level benchmark and to reduce in the case of two pipe stage 10.5% and three pipe stage as many as 33.4%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.66-66
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• 2001

새로운 마이크로프로세서의 설계, 최적화, 그리고 완성 후 어플리케이션의 작성 단계에서 칩의 명령어 집합 시뮬레이션은 필수적인 요소이다. 그러나, 기존의 시뮬레이션 툴들은 저 수준의 하드웨어 기술언어와 게이트 레벨 이하의 시뮬레이션으로 인해 시뮬레이터 구성과 실행 시에 상당한 시간적 지연을 초래하고 있다. 본 논문에서는 이러한 문제들을 해소하고 칩 제작과정에서 발생하는 잦은 설계 변경에 유연성 있게 대응할 수 있는 레지스터 전송 수준의 명령어 집합 시뮬레이터 생성기를 제안하며 그 설계 및 구현에 관해 기술한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.20-25
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• 2005

A high performance Viterbi decoder is designed using modified register exchange scheme and block decoding method. The elimination of the trace-back operation reduces the operation cycles to determine the merging state and the amount of memory. The Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoding methods in block decoding architectures. The elimination of trace-back also reduces the power consumption for finding the merging state and the access to the memory. The proposed decoder can be designed with emphasis on either efficient memory or low latency. Also, it has a scalable structure so that the complexity of the hardware and the throughput are adjusted by changing a few design parameters before synthesis.

• Journal of the Korean Society of Industry Convergence
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• v.2 no.2
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• pp.109-114
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• 1999

본 논문에서는 응용 주문형 집적회로 (ASICs)로 구현되는 신호처리기의 비용 예측 방법을 소개한다. 비용 예측은 디자인의 초기 단계에서 다양한 설계 사양들을 비교하여 성능과 비용 면에서 최적의 설계를 찾는데 도움을 준다. 본 비용 예측 방법은 Computer-Aided Design 도구들을 이용하여 시스템 동작 표현으로부터 시작하여 시스템 분할과 상위 수준 합성을 거쳐 레지스터 전송 수춘 단계에서 비용 예측을 실행한다. 사례 연구로 SWIR focal plane으로부터 생성되는 신호를 처리하는 신호처리기의 비용 예측을 실험한다. IBM 1.0 마이크론 기술의 CMOS 표준 셀을 적용하여 실험을 한 결과 각 채널로부터 전달되는 데이터를 실행하기 위해서는 3개의 칩이 필요했다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.220-228
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• 2001

Simulation of an instruction set is essential to design and optimize new microprocessors, and to develop application programs. Though many simulation tools are widely used, their low-level description and simulation make users construct simulators difficult and spend a lot of time for simulation. We developed an automatic generator of instruction set simulators that perform register-transfer-level simulation. This automatic generator might be adaptable so as to be suitable for new modification or different conditions in designing microprocessors. In this paper, we describe a structure of automatic generation system and an implementation details.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.1
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• pp.66-75
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• 2002

For the theoretical performance analysis of Viterbi Decoder for wireless LAN with data rate 12Mbps, code rate 1/2 and constraint length 7 defined in IEEE 802.11a, the transfer function is derived using Cramer's rule and the first-event error probability and bit error probability is derived under the AWGN. In the design process, input symbol is quantized into 16 steps for 4 bit soft decision and register exchange method instead of memory method is proposed for trace back, which enables the majority at the final decision stage. In the implementation, the Viterbi decoder based on parallel architecture with pipelined scheme for processing 12Mbps high speed data rate and AWGN generator are implemented using FPGA chips. And then its performance is verified in real time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.46-56
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• 2002

In this paper, we describe a hardware-software co-verification methodology and environment in developing a mobile station modem chip for cdma2000 1x which is one of the 3rd generation mobile communication standards. By constructing an efficient co-verification environment for a register-transfer-level hardware model and a physical-layer software model combining a channel link simulator and a versatile test-bench, we can drastically reduce both time and cost for developing a complex three-million-gate class system integrated circuit.