• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.1
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• pp.34-41
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• 2002

In the conventional rake receiver structure for the IS-95 CDMA system, each finger has its own time-deskew buffer or FIFO that aligns the multipath signals to the same timing reference in order to combine symbols. This architecture is not a burden to the rake receiver design mainly because of the small number and size of the buffers. However, the number and size of the buffers are significantly increased in the cdma2000 system which adopts multiple carriers and the small spreading gain for a higher rate in data services. In order to decrease the number of buffers, we propose a new model of the time-deskew buffers, which combines the symbols as well as realigns them at the same time. Our architecture reduces the hardware complexity of the buffers by about more than 60% and 70% compared with the conventional one when we consider each rake receiver has three and four independent fingers, respectively. Moreover, the proposed algorithm is very useful not only to the cdma2000 rake receiver but also to the receiver with many fingers in order to increase the BER performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.36-42
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• 2010

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically $log_2N$) as the FFT point-size (N) increases, the number of required registers (or, memories) increases linearly. In large point-size FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 38.5% area reduction compared with previous IFFT designs.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.2
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• pp.149-156
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• 2012

Support vector machines (SVMs) are well known for their pattern recognition capability, but proper care should be taken to alleviate their inherent implementation cost resulting from high computational intensity and memory requirement, especially in embedded systems where only limited resources are available. Since the memory requirement determined by the dimensionality and the number of support vectors is generally too high for a cache in embedded systems to accomodate, frequent accesses to the main memory occur inevitably whenever the cache is not able to provide requested data to the processor. These frequent accesses to the main memory result in overall performance degradation and increased energy consumption because a memory access typically takes longer and consumes more energy than a cache access or a register access. In this paper, we propose a technique that reduces the number of main memory accesses by optimizing the data access pattern of the SVM-based classifier in such a way that the temporal locality of the accesses increases, fully utilizing data loaded into the processor chip. With experiments, we confirm the enhancement made by the proposed technique in terms of the number of memory accesses, overall execution time, and energy consumption.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.2
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• pp.65-77
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• 2009

This paper proposes fast image processing algorithms using SSE (Streaming SIMD Extensions) instructions. The CPU's supporting SSE instructions have 128bit XMM registers; data included in these registers are processed at the same time with the SIMD (Single Instruction Multiple Data) mode. This paper develops new SIMD image processing algorithms for Mean filter, Sobel horizontal edge detector, and Morphological erosion operation which are most widely used in automated optical inspection systems and compares their processing times. In order to objectively evaluate the processing time, the developed algorithms are compared with OpenCV 1.0 operated in SISD (Single Instruction Single Data) mode, Intel's IPP 5.2 and MIL 8.0 which are fast image processing libraries supporting SIMD mode. The experimental result shows that the proposed algorithms on average are 8 times faster than the SISD mode image processing library and 1.4 times faster than the SIMD fast image processing libraries. The proposed algorithms demonstrate their applicability to practical image processing systems at high speed without commercial image processing libraries or additional hardwares.

• KIPS Transactions on Software and Data Engineering
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• v.2 no.8
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• pp.571-578
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• 2013

The IHO S-100 is a standard on the universal hydorgraphic data model for supporting information services that integrate various data in maritime and provide proper information for safety of vessels. The S-100 is used to develop S-10x product specifications which are standards on guideline for creation and delivery of specific data set in maritime. The product specification for feature-based data such as ENC(Electronic Navigational Chart) data includes a feature catalogue that describes characteristics of features in that feature-based data. The feature catalogue is developed by domain experts with knowledge on data of the target domain. However, it is not feasible to develop a feature catalogue according to the XML schema by manual. In the IHO TSMAD committee meeting, needs of developing technology on building feature catalogue has been discussed. Therefore, we present a feature catalogue builder that is a GUI(Graphic User Interface) system supporting domain experts to build feature catalogues in XML. The feature catalogue builder is developed to connect with the FCD(Feature Concept Dictionary) register in the IHO(International Hydrographic Organization) GI(Geographic Information) registry. Also, it supports domain experts to select proper feature items based on the relationships between register items.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.7 s.349
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• pp.93-103
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• 2006

Network solutions for protecting against worm attacks that complement partial end system patch deployment is a pressing problem. In the content-based worm filtering, the challenges focus on the detection accuracy and its performance enhancement problem. We present a worm filter architecture using the bloom filter for deployment at high-speed transit points on the Internet, including firewalls and gateways. Content-based packet filtering at multi-gigabit line rates, in general, is a challenging problem due to the signature explosion problem that curtails performance. We show that for worm malware, in particular, buffer overflow worms which comprise a large segment of recent outbreaks, scalable -- accurate, cut-through, and extensible -- filtering performance is feasible. We demonstrate the efficacy of the design by implementing it on an Intel IXP network processor platform with gigabit interfaces. We benchmark the worm filter network appliance on a suite of current/past worms, showing multi-gigabit line speed filtering prowess with minimal footprint on end-to-end network performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.14-23
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• 2002

Two implementation methods for SOVA (Soft Output Viterbi Algorithm)of Turbo decoder are applied and verfied. The first method is the combination of a trace back (TB) logic for the survivor state and a double trace back logic for the weight value in two-step SOVA. This architecure of two-setp SOVA decoder allows important savings in area and high-speed processing compared with that of one-step SOVA decoding using register exchange (RE) or trace-back (TB) method. Second method is adjusting the reliability value with a scaling factor between 0.25 and 0.33 in order to compensate for the distortion for a rate 1/3 and 8-state SOVA decoder with a 256-bit frame size. The proposed schemes contributed to higher SNR performance by 2dB at the BER 10E-4 than that of SOVA decoder without a scaling factor. In order to verify the suggested schemes, the SOVA decoder is testd using Xillinx XCV 1000E FPGA, which runs at 33.6MHz of the maximum speed with 845 latencies and it features 175K gates in the case of 256-bit frame size.

• Journal of The Korean Association For Science Education
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• v.32 no.7
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• pp.1251-1268
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• 2012

This study investigated several cases of interactive learning mediated by exhibits in a natural history hall during visits by middle school students. Five visiting cases were selected, in which visitors engaged actively in the interactions between them. Each visiting case was analyzed in terms of visiting discourse register and the modes of interaction in order to understand both visitors' meaning-making processes through the discourse flow and the characteristics of visiting discourse according to the features of exhibits. Results were as follows. The information provided in the exhibits was used as THEMEs in visitors' discourse and the visitors presented their information on the THEMEs as RHEMEs. The visitors made their own meaning for the exhibits by exchanging their information with each other. Interrogative sentences on the exhibit panels allowed visitors to make arguments. Similar exhibits displayed together helped visitors to compare those exhibits. These two features of the exhibits facilitated visitors' meaning-making processes in the natural history hall. The modes of interaction between visitors mediated by the exhibits showed that the information itself from the exhibits as well as visitors' opinion on the exhibits were frequently used as the elements for in-depth cognitive social interactions that allowed the visitors to construct meaning. Based on these results, we discussed that understanding in detail how visitors choose information from exhibits and construct visiting discourse is very important to improve visitors' collaborative science learning at a natural history hall.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1393-1398
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• 2009

Conventionally, etching is first considered for microelectronics fabrication process and is specially important in process of a-Si:H thin film transistor for LCD. In this paper, we stabilize properties of device by development of wet and dry etching process. The a-Si:H TFTs of this paper is inverted staggered type. The gate electrode is lower part. The gate electrode is formed by patterning with length of 8 ${\mu}$m${\sim}$16 ${\mu}$m and width of 80${\sim}$200 ${\mu}$m after depositing with gate electrode (Cr) 1500 ${\AA}$under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photo resistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN:H (2000 ${\mu}$m), a-Si:H(2000 ${\mu}$m) and n+a-Si:H (500 ${\mu}$m), We have deposited n-a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. In the fabricated TFT, the most frequent problems are over and under etching in etching process. We were able to improve properties of device by strict criterion on wet, dry etching and cleaning process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.6
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• pp.1099-1103
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• 2007

TFT's have been intensively researched for possible electronic and display applications. Through tremendous engineering and scientific efforts, a-Si:H TFT fabrication process was greatly improved. In this paper, the reason on defects occurring at a-Si:H TFT fabrication process is analyzed and solved, so a-Si:H TFT's yield is increased and reliability is improved. The a-Si:H TFT of this paper is inverted staggered type TFT. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr). We have fabricated a-SiN:H, conductor, etch-stopper and photo-resistor on gate electrode in sequence, respectively. We have deposited n+a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-slower pattern. The NPR layer by inverting pattern of upper Sate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFT made like this has problems at photo-lithography process caused by remains of PR. When sample is cleaned, this remains of PR makes thin chemical film on surface and damages device. Therefor, in order to improve this problem we added ashing process and cleaning process was enforced strictly. We can estimate that this method stabilizes fabrication process and makes to increase a-Si:H TFT's yield.