• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.8
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• pp.639-647
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• 1990

Dynamic time warp(DTW) needs for interative calculations and the design of PE cell suitable for the operations is very important. Accordingly, this paper aims at the real time recognition design which enables large dictionary hardware realization using DTW algorithm. The DTW PE cell is seperated into three large blocks. "MIN" is the one block for counting accumulated minimum distance, "ADD" block calculates these minimum distances, and "ABS" seeks for the absolute values to the total sum of local distances. We have accomplisehd circuit design and verification for the MIN blocks, and performed MIN layout and DRC(design rule check) using 3um CMOS N-Well rule base.ing 3um CMOS N-Well rule base.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.838-841
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• 2007

In this study, we implemented a $17^*17b$ binary digital multiplier using radix-4 Booth's algorithm. Two stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. To evaluate the circuit, several MPW chips were fabricated using Hynix 0.6-um 3M N-well CMOS technology. Also we proposed an efficient test methodology and did fault simulations. The chip contains 9115 transistors and the core area occupies about $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.6
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• pp.62-66
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• 1982

A method finding out routability for unrouted signal lines and rerouting those which are turned out to be able to route in layout design of LSI is described. In this paper the problems of finding two-disjoint Paths represented by an undirected graph G=(V,E), where V,E are sets of vertices and edges respectively, are studied. The existence of two-disjoint paths from s1, to t1, (called P1) and from S2 to T2 (called P2) indicated by the four vertices on the graph s1, t1, s2, t2 $\in$ V means that two distinct signal lines exist in layout design. It turns out that the proposed time complexity in the algorithm is O (IVI x IEI).

• Proceedings of the Korea Information Processing Society Conference
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• 2003.11a
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• pp.339-342
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• 2003

배치는 칩의 성능 및 레이아웃에 결정적인 영향을 주는 요인으로써 크게 광역배치와 상세배치 두단계를 거쳐 이루어지며 수년 동안 다양한 기법들이 개발되어 왔다. 본 논문에서는 표준 셀 배치를 개선하기 위한 동적 프로그래밍 기법을 이용한 최적 인터리빙 알고리즘을 확장하여 선을 동일 행 내에서만 움직이던 한계점을 극복하여 서로 다른 행 사이에서도 움직일 수 있도록 하였다. 즉, 셀들은 주어진 배치 내에서 임의의 위치로 움직일 수 있어 배치가 더욱 효율적으로 최적화 될 수 있도록 하였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.85-93
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• 1984

In the paper, a new constructive initial placement algorithm is proposed in computer aided layout design in LSI. An useful object function are proposed to place the modules in logic design diagram laid down by manual to the fixed chip, reflecting the relative positions between modules and cells, and then an initial placement are determined by the function. In order to show the usefulness of the proposed method, it was compared with clustering development method in maximum cut numbers and total routing lengths by program experiments.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10d
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• pp.160-162
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• 2002

지리정보시스템(GIS)에서 사용하는 지도는 여러 가지 목적의 응용 프로그램이나 지도의 축척등에 의해 서 다양하게 나타난다. 본 논문은 지리정보 시스템에 사용되는 지도중에서 관광안내지도를 대상으로 최적의 레이블링과 아이콘 표시방법을 통하여 관광지도 정보를 최적화하여 표현하기 위한 논문이다. 이를 위하여 서울시내의 여러 가지 관광버스의 노선도를 분석하여 이를 최적화된 방법으로 배치하고 표현하는 위한 방법을 연구하였다. 복잡한 버스의 노선은 주요 시설물을 중심으로 선분 간략화 알고리즘을 통하여 간략화 하였으며 간략화된 노선에서 중첩되는 레이블은 레이블 재배치 알고리즘을 이용하여 재배열하였다. 이러한 방법을 통하여 지리정보 데이터베이스로부터 자동화된 방식으로 구조화된 지도를 손쉽게 생성하는 방법을 제시한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.433-434
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• 2009

본 논문에서는 그리드 형태의 레이아웃을 갖는 도시지역 신호등망에 대해 효율적인 라우팅 기법을 개발하고 평가할 수 있는 프레임워크를 구성한다. 신호등망은 다중인접 그래프로 자료구조화하며 직접 통신이 가능한 노드들에게는 링크가 추가되었다. 또 전송 전에 channel probing에 의해 경로를 선택하는 split-merge 방식을 고려하여 가상링크를 그래프에 추가하고 이의 비용을 산정한다. 이후 Dijkstra 알고리즘과 같이 프레임워크에서 제공되는 경로 탐색 기능으로 하여금 가상링크를 포함한 경로를 찾은 다음 최종적으로 이 경로를 기반으로 가상링크를 실제링크로 변환하도록 하였다. 이를 바탕으로 슬롯 오류 비율을 변화시켜가면서 실제 전송 성공률을 측정할 수 있으며 새로운 경로배정 알고리즘 개발을 위한 피드백을 제공할 수 있다.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.4
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• pp.97-102
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• 2001

In computer-aided design, partitioning is task of clustering objects into groups to that a given objection function is optimized It is used at the layout level to fin strongly connected components that can be placed together in order to minimize the layout area and propagation delay. Partitioning can also be used to cluster variables and operation into groups for scheduling and unit selection in high-level synthesis. The most popular algorithms partitioning include the Kernighan-Lin algorithm Fiduccia-Mattheyses heuristic and simulated annealing In this paper we propose a genetic algorithm searching solution space for the circuit partitioning problem. and then compare it with simulated annealing by analyzing the results of implementation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.1
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• pp.477-483
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• 2019

In this paper, we propose vanishing-point position-improvement algorithms by using multiple images and a homography matrix. Vanishing points can be detected from a single image, but the positions of detected vanishing points can be improved if we adjust their positions by using information from multiple images. More accurate indoor space information detection is possible through vanishing points with improved positional accuracy. To adjust a position, we take three images and detect the information, detect the homography matrix between the walls of the images, and convert the vanishing point positions using the detected homography. Finally, we find an optimal position among the converted vanishing points and improve the vanishing point position. The experimental results compared an existing algorithm and the proposed algorithm. With the proposed algorithm, we confirmed that the error angle to the vanishing point position was reduced by about 1.62%, and more accurate vanishing point detection was possible. In addition, we can confirm that the layout detected by using improved vanishing points through the proposed algorithm is more accurate than the result from the existing algorithm.

• Journal of Korea Multimedia Society
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• v.7 no.10
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• pp.1339-1353
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• 2004

< TABLE > tags in HTML documents are widely used for formatting layout of Web documents as well as for describing genuine tables with relational information. As a prerequisite for information extraction from the Web, this paper presents an efficient method for sophisticated table detection. The proposed method consists of two phases: preprocessing and attribute-value relations extraction. For the preprocessing where genuine or ungenuine tables are filtered out, appropriate rules are devised based on a careful examination of general characteristics of < TABLE > tags. The remaining is detected at the attribute-value relations extraction phase. Specifically, a value area is extracted and checked out whether there is a syntactic coherency Futhermore, the method looks for a semantic coherency between an attribute area and a value area of a table that may be inappropriate for the syntactic coherency checkup. Experimental results with 11,477 < TABLE > tags from 1,393 HTML documents show at the method has performed better compared with previous works, resulting in a precision of 97.54% and a recall of 99.22% in average.