• Journal of the Korean Institute of Intelligent Systems
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• v.16 no.5
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• pp.627-634
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• 2006

We have proposed the methods how to control the slope of CMOS inverter's characteristic and how to shift it in y axis. We control the MOS transistor threshold voltage for these methods. By observing that two transistors are in saturation region at the center of the CMOS inverter's characteristic, we have presented how to make the characteristic for one pole neuron. The circuit level simulation is used for verifying the proposed method. PSpice(OrCAD Co.) is used for circuit level simulation.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.297-298
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• 2016

본 논문에서는 제안하는 컨버터와 인버터의 회로를 통합하여 다중레벨의 출력 전압과 커패시터의 전압 균등화 동작을 부스트와 차지펌프 회로를 이용하여 고효율의 회로를 구성하였다. 또한 결합 인덕터를 사용함으로써 누설인덕턴스를 최소화 할 뿐만 아니라 추가적인 전하균등화 회로를 추가하지 않음으로 써 가격에서도 유리함을 제공한다. 부스트-차지펌프회로와 멀티레벨 인버터가 결합된 새로운 구조를 제안하고 이를 수식적으로 정리하고 시뮬레이션과 실제 하드웨어를 통하여 검증하였다.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1707_1708
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• 2009

Unit master control(UMC)는 발전소의 요구 부하신호를 설정하는 최상위의 제어레벨이며 UMC의 설정값은 자동급전 지령신호(Automatic Dispatch System : ADS) 또는 운전원이 설정하는 값에 따라 보일러 및 터빈 Master에 Unit 요구 신호를 출력하여 하위제어 레벨인 공기, 연료, 급수 등을 조절할 수 있는 기기에 Unit 부하 요구 신호(Unit Load Demand : ULD)에 따라 제어 되도록 하는 방법으로서, Unit 목표부하 설정, Unit 목표부하 상/하한 제한, 목표부하 변화율 제한, 주파수 보정, Runback/Rundown/ Runup, 보일러 및 터빈 Demand 신호생성의 기능을 가지고 있다.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06a
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• pp.208-210
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• 2006

프로세서의 온도를 낮추기 위한 컴퓨터 과학적 접근법으로는 가변전압주파수조절(DVFS), 파이프라인에서 더 이상 명령어를 수행하지 못하게 하는 방법(pipeline throttling) 등이 있다. 하지만, 이러한 해결책은 대부분 소수의 은도 센서가 내장되어 있어 이를 기반으로 온도를 제어하였다. 본 논문에서는 실제 Pentium 4에 기반한 시스템을 통하여, 운영체제 레벨의 가변주파수방법(DFS)을 이용한 스케줄링이 여러 개의 온도센서를 사용하여 국지화된 뜨거운 부분(localized hotspot)을 얼마나 효율적으로 온도를 제어할 수 있는지를 보여준다.

• Journal of the Korea Society of Computer and Information
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• v.13 no.1
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• pp.81-88
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• 2008

In the game balancing. it is so difficult to choose suitable arms among various actions, or arms and to accurately calculate to which level we adjust the balance. The fuzzy method can be properly used in a particular environment which cannot be correctly processed in mathematics or in lessening the time-consuming problems during the accurate number crunching. Because a variety of actions, relations with opponents. previous battle experiences etc. are not easy to be reflected in every occasion, the fuzzy method could be useful in these cases. When the balancing is needed. the data which have been played to that Point are processed by the fuzzy function and calculated to adapt intensity to each action. The ability of characters is regulated in this process. To demonstrate the efficiency of this method. I would like to make clear the excellence of fuzzy method through the following five experiments; a case with invariable ability adjustment, a case adjusted by a randomly chosen action, a case with the strongest weapon selection. a case with the weakest weapon selection and a case with the fuzzy method application.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.76-80
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• 2007

In this paper, the PAE (Power Added Efficiency) and the linearity of the Doherty amplifier has been improved using dual bias control and PBG (Photonic BandGap) structure. The PBG structure has used to implement on output matching circuit and dual bias control has applied to improve the PAE of the Doherty amplifier at a low input level by applying it to a carrier amplifier. The Doherty amplifier using the proposed structure has improved PAE by 8% and 5dBc of IMD3 (3rd Inter-Modulation Distortion) compared with those of the conventional class AB amplifier. In addition to, it has been evident that the designed the structure has showed more than a 30% increase in PAE for flatness over all input power level.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.8 s.111
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• pp.707-712
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• 2006

In this paper, dual bias control circuit and PBG(Photonic BandGap) structure have been employed to improve PAE(Power Added Effciency) of the Doherty amplifier on Input power level. The gate and drain bias voltage has been controlled with the envelope of the input RF signal and PBG structure has been employed on the output port of Doherty amplifier. The proposed Doherty amplifier using dual bias controlled circuit and PBG has been improved the average PAE by 8%, $IMD_3$ by -5 dBc. And proposed Doherty amplifier has a high efficiency more than 30% on overall input power level, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.10-15
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• 2012

This letter proposes a low-leakage SRAM using power-gating and voltage-level control. The power-gating scheme significantly reduces leakage power by shutting off the power supply to blank memory cell blocks. The voltage-level control scheme saves leakage power by raising the ground line voltage of SRAM cells and word line decoders in data-stored memory cell blocks. A $4K{\times}8bit$ SRAM chip was fabricated using a 1.2V $0.13{\mu}m$ CMOS process. The leakage powers are $1.23{\sim}9.87{\mu}W$ and $1.23{\sim}3.01{\mu}W$ for 0~100% memory usage in active and sleep modes, respectively. During the sleep mode, the proposed SRAM consumes 12.5~30.5% leakage power compared to the conventional SRAM.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.490-492
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• 2010

A swing level controlled voltage-mode transmitter is proposed to support a stub series-terminated logic channel with center-tapped termination. This transmitter provides a swing level control to support the diagnostic mode and improve the signal integrity in the absence of the destination termination. By using the variable parallel termination, the proposed transmitter maintains the constant output impedance of the source termination while the swing level is controlled. Also, the series termination using an external resistor is used to reduce the impedance mismatch effect due to the parasitic components of the capacitor and inductor. To verify the proposed transmitter, the voltage-mode driver, which provides eight swing levels with the constant output impedance of about $50{\Omega}$, was implemented using a 70nm 1-poly 3-metal DRAM process with a 1.5V supply. The jitter reduction of 54% was measured with the swing level controlled voltage-mode driver in the absence of the destination termination at 1.6-Gb/s.

• Proceedings of the KIPE Conference
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• 2011.11a
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• pp.209-210
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• 2011

본 논문은 3레벨 NPC 인버터의 중성점 전위 변동 시 퍼지제어기를 이용한 중성점 전위 제어 방법을 제안한다. 오프셋 전압을 퍼지제어기의 입력으로 하여 공간벡터의 스위칭 타이밍의 조절변수를 출력함으로써 기존의 오프셋 전압의 복잡한 수학적 모델링 없이 쉽고 간단하게 중성점 전압을 제어한다. 제안하는 제어기법의 우수성을 보이기 위하여 10kW급 계통연계 3-레벨 NPC인버터 모델을 기반으로 시뮬레이션을 수행하였다.