• Journal of KIISE:Software and Applications
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• v.30 no.7_8
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• pp.599-609
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• 2003

Video abstraction is a process to pick up some important shots on a video, while the important shots might vary on the persons subjectivity. Previous works on video abstraction use only one low level feature to choose an important shot. This thesis proposes an abstraction scheme that selects a set of shots which simultaneously satisfies the desired features(or objective functions) of a good abstraction. Since the complexity of the computation to find a set of shots which maximizes the sum of object function values is $0({2^n})$, the proposed .scheme uses a simulated annealing based searching method to find the suboptimal value within a short period of time. Upon the experimental results on various videos, we could argue that the proposed abstraction scheme could produce a reasonable video abstraction. The proposed abstraction scheme used to build a digital video library.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.169-170
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• 2018

이진체 상의 타원곡선 B-233을 지원하는 타원곡선 암호 프로세서를 32-비트 워드기반 몽고메리 곱셈기를 이용하여 설계하였다. 스칼라 곱셈을 위해 수정된 몽고메리 래더 (Modified montgomery ladder) 알고리즘을 적용하여 단순 전력분석에 내성을 갖도록 하였으며, Lopez-Dahab 투영 좌표계와 페르마의 소정리(Fermat's little theorem)를 적용하여 하드웨어 자원 소모가 큰 나눗셈과 역원 연산을 제거하여 저면적으로 설계하였다. 설계된 ECC 프로세서는 Xilinx ISim을 이용하여 기능검증을 하였으며, $0.18{\mu}m$ CMOS 셀 라이브러리로 합성한 결과 100 MHz의 동작 주파수에서 9,614 GEs와 4 Kbit RAM으로 구현되었으며, 최대 동작 주파수는 125 MHz로 예측되었다.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.4
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• pp.67-75
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• 2020

In this paper, by applying LCP substrate, the capacitor and inductor are implemented with a variety of value that can be used in 35 GHz circuits. Depending on how to apply it to the circuit, it is required high value by designing the basic structures such as electrode capacitor and spiral inductor. However they are not available in high-frequency domain, because their SRF(Self-Resonant Frequency) is lower than the frequency of 35-GHz. By finding the limit, this paper devised classifying passive devices for the DC and the high-frequency domain. The basic structure is suitable for DC and microstrip λ/8 length stub structure can be used for high-frequency. The open and short stub structure operate as a capacitor and inductor respectively in the frequency of 35 GHz. If their impedance is known, it is possible to extract the value through the impedance-related equation. By producing with the permittivity 2.9 LCP substrate, the basic structure which are available in the DC constituted a library of capacitance of 1.12 to 13.9 pF and inductance of 0.96 to 4.69 nH, measured respectively. The stub structure available in the high-frequency domain were built libraries of capacitance of 0.07 to 2.88 pF and inductance of 0.34 to 1.27 nH, calculated respectively. The measurements have proven how to diversify value, so libraries can be built more variously. It is possible to integrate with the operation circuit of TRM(Transmit-Receive Module) for the frequency 35-GHz, it will be an alternative to the passive devices that can be properly utilized in the circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.32-36
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• 2008

Multiplierless FIR filters can be designed by only adders using Common Subexpression algorithm. It has small area compared with filter which using multipliers. But it has long operation time because of carry ripple from the adder. In this paper, when the subexpressions are added in multiplier less filters, the number of subexpressions maintains 2 until final addition to avoid carry ripple of the addition, so the subexpression addition time of the filter can be reduced. To verify proposed method, subexpression adder circuit of the FIR filter is designed using given example of paper. The designed filter was synthesized using Hynix 0.18um process. By Synopsys simulation results, it is shown that by the proposed method, area, propagation delay time can be reduced up to 53.2%, 57.9% compared with conventional design method which using pipeline.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.686-689
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• 2009

This paper describes a scalar multiplier for Elliptic curve cryptography. The scalar multiplier has 163-bits key size which supports the specifications of smart card standard. To reduce the computational complexity of scalar multiplication on finite field $GF(2^{163})$, the Non-Adjacent-Format (NAF) conversion algorithm based on complementary recoding is adopted. The scalar multiplier core synthesized with a $0.35-{\mu}m$ CMOS cell library has 32,768 gates and can operate up to 150-MHz@3.3-V. It can be used in hardware design of Elliptic curve cryptography processor for smart card security.

• Proceedings of the KAIS Fall Conference
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• 2011.12b
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• pp.434-437
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• 2011

본 논문에서는 H.264/AVC 복호기의 성능을 향상시키기 위해 병렬 역양자화 구조와 역변환 구조를 제안한다. 제안하는 역양자화 구조는 공통 연산기를 사용하여 계산 복잡도를 감소시키고, 4개의 공통연산기를 사용하여 역양자화 수행 사이클 수를 1 사이클로 감소시킨다. 제안하는 역변환 구조는 4개의 변환 연산기를 사용하여 역변환 연산을 수행하는데 2 사이클이 소요된다. 또한 제안하는 구조는 역양자화 연산과 수평 역변환 연산을 동시에 수행하는 병렬 구조를 채택하여 역양자화 및 역변환 수행 사이클 수를 2 사이클로 감소시킨다. 제안하는 구조를 Magnachip 0.18um CMOS 공정 라이브러리를 이용하여 합성한 결과 1.5MHz의 동작 주파수에서 게이트 수는 14,173이고, 표준 참조 소프트웨어 JM 9.4에서 추출한 데이터를 이용하여 성능을 측정한 결과 제안하는 구조의 수행 사이클 수가 기존 구조 대비 38.74% 향상되었다.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2132-2135
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• 2003

본 논문에서는 고정소수점 DSP로 구현한 실시간 MP3 오디오 부호화기에 사용되는 초월함수용 하드웨어 가속기 구조를 제안한다. 구현된 하드웨어 가속기는 MP3 부호화 성능을 저하시키는 초월함수 연산오차에 강인하도록 설계되었다. 제안된 가속기의 연산오차는 Q1.23 고정소수점 출력에서 2비트, 즉 2/sup -21/ 까지의 연산오차를 가진다. LAME 부호화기[5]심리음향 모델의 SMR 오차는 테이블 보간법[4]을 사용할 경우에 비해 4dB이상 향상되었으며, 연산량은 총 4 MIPS 감소하였다. 제안한 하드웨어 가속기는 Verilog HDL로 기술되었으며, SYNOPSYS에서 0.18㎛ CMOS 표준 셀 라이브러리 공정으로 합성되었다. 합성 면적은 7514 게이트이며 초월함수 연산에 대한 동작속도는 3 사이클이다.

• Journal of Korean Library and Information Science Society
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• v.39 no.2
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• pp.169-186
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• 2008

Social Network has been known as friendship basis human relation service in online network. But a broad sense of Social Network can be explained as a mechanism which makes web evolve to information-ecosystem by human relation and network data which has been generated by the mass of people's cooperation and interchange. Social Network has been expanding their domain from friendship basis relation service to broad social relationship focus of matter of concern. It has been applied to diverse domain. Library community begins to take an interest in Social Network concept to apply user's interchange for information. This paper considers the concept of Social network and it's appliance to a library service. For the more, suggest basic element for vitalizing library user's Social network.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.2
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• pp.108-113
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• 2009

FIR upsampling circuit generates output data L times faster than input data. For efficient implementation of upsampler, FT filter stages Noble identity theory. In this paper, we propose a method that one of the divided filter stages is removed by making Phase delay to integer number. 192taps 2-times upsampler used in CDtoDAT is designed using proposed method. The designed circuit is synthesized using Hynix 0.18um process. By the simulation results, it is shown that the proposed method leads to up to 48%, 43% and 99.9% and 68% reduction in area, power consumption and maximum phase delay error and maximum ripple error compared with conventional method.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.5
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• pp.496-505
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• 2000

Clusters of workstations (COW) are becoming an attractive option for parallel scientific computing, a field formerly reserved to the MPPs, because their cost-performance ratio is usuallybetter than that of comparable MPPS, and their hardware and software can be easily enhanced to thelatest generations. In this paper we present the design and implementation of our runtime library forclusters of workstations, called "Collective I/O Clustering". The library provides a friendlyprogramming model for the I/O of irregular applications on clusters of workstations, being completelyintegrated with the underlying communication and I/O system. In the collective I/O clustering, two I/Oconfigurations are possible. In the first I/O configuration, all processors allocated can act as I/Oservers as well as compute nodes. In the second I/O configuration, only a subset of processors canact as I/O servers, The compression and software caching facilities have been incorporated into thecollective 1/0 clustering to optimize the communication and I/O costs. All the performance results wereobtained on the IBM-SP machine, located at Argonne National Labs.