Journal of the Institute of Electronics Engineers of Korea SP (대한전자공학회논문지SP)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Efficient FIR Upsample Circuit

효율적인 FIR Upsample 회로

  • Kim, Yong-Eun (Div. of Electronic & Information Engineering Chonbuk University)
  • 김용은 (전북대학교 전자정보공학부)
  • Published : 2009.03.25
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Abstract

FIR upsampling circuit generates output data L times faster than input data. For efficient implementation of upsampler, FT filter stages Noble identity theory. In this paper, we propose a method that one of the divided filter stages is removed by making Phase delay to integer number. 192taps 2-times upsampler used in CDtoDAT is designed using proposed method. The designed circuit is synthesized using Hynix 0.18um process. By the simulation results, it is shown that the proposed method leads to up to 48%, 43% and 99.9% and 68% reduction in area, power consumption and maximum phase delay error and maximum ripple error compared with conventional method.

FIR upsampler는 입력 데이터 보다 L배 빠른 출력 신호를 생성한다. Upsampler의 효율적인 구현을 위해 일반적으로 Noble identity 공식을 이용하여 L개로 필터단을 나눈다. 본 논문에서는 나누어진 필터단 1개의 위상 지연을 정수로 만들어 필터단 1개를 제거하는 방법을 제안하였다. 제안한 방법을 이용하여 CDtoDAT에 이용되는 192탭 2배 upsampler를 하이닉스 0.18라이브러리를 이용하여 설계할 때 기존 회로에 비하여 면적, 파워, 최대위상지연에러, 최대리플에러에서 48%, 43%, 99.9%, 68% 만큼 효율적임을 확인하였다.

Keywords

References

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