• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.96-102
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• 2014

In this paper, we proposed new dual-rail data encoding that mixed 4-phase handshaking protocol and 2-phase handshaking protocol for asynchronous system design to reduce signal activities and power consumption. The dual-rail data encoding 4-phase handshaking protocol should leat to much signal activities and power consumption by return to space state. Ideally, the dual-rail data encoding 2-phase handshaking protocol should lead to faster circuits and lower power consumption than the dual-rail 4-phase handshaking protocol, but can not designed using standard library. We use a benchmark circuit that contains a multiplier block, an adder block, and latches to evaluate the proposed dual-rail data encoding. The benchmark circuit using the proposed dual-rail data encoding shows an over 35% reduction in power consumption with 4-phase dual-rail data encoding.

• Journal of the Korea Society for Simulation
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• v.26 no.2
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• pp.19-29
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• 2017

System Entity Structure/Model Base (SES/MB) enhances organizing model families and storing and reusing model components in the multifaceted system modeling. However, the real world can be described not only an individual system but also a collection of those systems, which is called system of systems (SoS). Because SES/MB has a limitation to simulate the SoS using HLA/RTI, an extended framework is required to simulate it. Therefore, this paper proposes System of Systems Entity Structure/Federate Base (SoSES/FB) for simulation in a distributed environment (HLA/RTI). The proposed method provides the library of federates (FB) and System of System Entity Structure (SoSES) formalism, which represents structural knowledge of a collection of simulators. It also provides a methodology for the development process of distributed simulation. The paper introduces the anti-missile defense simulation using the proposed SoSES/FB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.601-609
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• 2002

The efficient Viterbi decoder that supports full data-rate output of DAB system was proposed. Viterbi decoder consumes lots of computational load and should be designed to be fast specific hardware. In this paper, SST scheme was adopted for Viterbi decoder with puncturing to reduced the power consumption. Puncturing vector tables are modified and re-arranged to be designed by a hardwired logic to save the system area. New re-scaling scheme which uses the fact that the difference of the maximum and minimum of the path metric values is bounded is proposed. The proposed re-scaling scheme optimizes the wordlength of path metric memory and greatly reduces the computational load for re-scaling by controlling MSB of path metric memory. Another saving of computation is done by proposed algorithm for branch metric calculation, which makes use of pre-calculated metric values. The designed Viterbi decoder was synthesized using SAMSUNG 0.35$\mu$ standard cell library and occupied small area and showed lower power consumption.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2569-2578
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• 2009

Core-A microprocessor is the all-Korean product designed as 32-bit embedded RISC microprocessor developed by KAIST and supported by the Industrial Property Office. This paper analyze Core-A microprocessor architecture and proposes efficient method to interface Core-A microprocessor with coprocessor. To verify proposed interfacing method, the AES cryptography processor that has 128-bit key and block size is used as a coprocessor. Coprocessor and AES are written in Verilog-HDL and verified using Modelsim simulator. It except AES module consists of about 3,743 gates and its maximum operating frequency is about 90Mhz under 0.35um CMOS technology. The proposed coprocessor interface architecture is efficiency to send data or to receive data from Core-A to coprocessor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7B
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• pp.647-659
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• 2003

LPM(Longest Prefix Matching)searching in If address lookup is a major bottleneck of IP packet processing in the high speed router. In the conventional lookup table for the LPM searching in CAM(Content Addressable Memory) the complexity of fast update take 0(1). In this paper, we designed pipeline architecture for fast update of 0(1) cycle of lookup table and high throughput and low area complexity on LPM searching. Lookup-table architecture was designed by CAM(Content Addressable Memory)away that uses 1bit RAM(Random Access Memory)cell. It has three pipeline stages. Its LPM searching rate is affected by both the number of key field blocks in stage 1 and stage 2, and distribution of matching Point. The RTL(Register Transistor Level) design is carried out using Verilog-HDL. The functional verification is thoroughly done at the gate level using 0.35${\mu}{\textrm}{m}$ CMOS SEC standard cell library.

• The KIPS Transactions:PartA
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• v.19A no.4
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• pp.175-180
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• 2012

This paper describes the design of high-performance pedestrian and vehicle detection circuit using the Haar-like features. The proposed circuit uses a sliding window for every image frame in order to extract Haar-like features and to detect pedestrians and vehicles. A total of 200 Haar-like features per sliding window is extracted from Haar-like feature extraction circuit and the extracted features are provided to AdaBoost classifier circuit. In order to increase the processing speed, the proposed circuit adopts the parallel architecture and it can process two sliding windows at the same time. We described the proposed high-performance pedestrian and vehicle detection circuit using Verilog HDL and synthesized the gate-level circuit using the 130nm standard cell library. The synthesized circuit consists of 1,388,260 gates and its maximum operating frequency is 203MHz. Since the proposed circuit processes about 47.8 $640{\times}480$ image frames per second, it can be used to provide the real-time detection of pedestrians and vehicles.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2914-2922
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• 1997

For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus needs to increase the system performance of multiprocessor environment. VME(versa module european package format) bus is appropriated to the standard bus but has features of small package and low board density. Beside, the density of board and semiconductor have grown to become significant issues that affect development time, project cost and field diagnostics. To fit this trend, in this paper, we composed Revision C.1 (IEEE std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between, VMEbus and several control modules Also the designed, VME system controller is implemented on FPGA that can be located even into slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, we confirmed the most important that is the operation of Bus timer about Bus error signal should occur within $56{\mu}m$, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.

• The Transactions of the Korea Information Processing Society
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• v.4 no.10
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• pp.2521-2532
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• 1997

The next generation internet protocol, IPv6, have been developed by the IETF according to the requirements of enhancement of classic IP protocols to satisfy the lack of Internet address space as well as the support of multimedia applications. This paper presents an implementation of IPv6 protocols on the Windows NT kernel environment. In this work, we developed and also tested the basic functions, required for operating as an IPv6 host, such as IPv6 header processing, IPv6 address handling, control message processing, group membership processing and neighbor discovery functions. The implemented IPv6 protocol driver module is connected to the lower network interface card through NDIS, a standard network interface. And this driver module that operates within kernel, is implemented as it is connected to upper user applications and lower NDIS using dispatch and lower-edge functions. The developed IPv6 protocol driver can provide not only enhanced performance because it is implemented in kernel mode, but also convenience of usage to the application developers because it gives user interface as a dynamic link library.

• KIPS Transactions on Computer and Communication Systems
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• v.6 no.8
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• pp.329-342
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• 2017

Recently, interest and investment in the Internet of Things (IoT) have increased significantly, and security issues are constantly being raised. As a solution, the IETF ACE Working Group is establishing the ACE framework standard, which is a new security framework for various constrained IoT environments based on the existing OAuth 2.0. However, additional work is required to apply the ACE framework, which proposes a new lightweight security system, to the existing Internet environment, and this additional cost is a factor that hinders the application of OAuth 2.0 to the IOT environment. Therefore, we propose an IoT authentication framework based on OAuth 2.0's existing development motivation, and implement a proposal framework based on CoAPthon and analyze its performance.

• Journal of the Society of Disaster Information
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• v.17 no.2
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• pp.329-340
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• 2021

Purpose: In this paper, using artificial neural network algorithm, the Korean Peninsula was analyzed for drought vulnerable areas by predicting weather data changes. Method: Monthly cumulative precipitation data were utilized for research areas considering the specific nature areas, and weather data prediction through artificial neural network algorithm was carried out using statistical program R. The predicted data were applied to the Standardized Precipitation Index (SPI) to analyze drought vulnerable areas in the Korean Peninsula. Result: In this paper, the correlation coefficient values between real and predicted data are found to be 0.043879 higher on average than the regression results, using artificial neural network algorithms. Conclusion: The results of the research are expected to be used as basic research materials for responding to drought.