• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.89-96
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• 2002

In this paper, the ADI(Adaptive De-interlacing) algorithm is proposed, which improves visually and subjectively horizontal and vertical edges of the image processed by the ELA(Edge Line-based Average) method. This paper also proposes a VLSI architecture for the proposed algorithm and the architecture designed through the full custom CMOS layout process. The proposed algorithm is verified using C and Matlab and implemented using $0.6{\mu}m$ 2-poly 3-metal CMOS standard libraries. For the circuit and logic simulation, Cadence tool is used.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.44-51
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• 2010

This paper proposes the architecture of high-performance Viterbi decoder circuit. The proposed circuit does not require additional memory to calculate the branch metrics because it uses the characteristics of the branch data. The speed of the Viterbi decoder circuit is increased up to 75% by rearranging the path metric data in SRAM and registers properly for fast add-compare-select operations. We described the proposed Viterbi decoder circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The synthesized circuit consists of 8,858 gates and its maximum operating frequency is 130MHz.

• Journal of The Korean Association of Information Education
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• v.15 no.2
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• pp.287-294
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• 2011

In this paper, we suggest performance enhanced Mobile Web service architecture. Mobile Web Services are new technology that integrates different applications to provide interoperability. SOAP is a lightweight message exchanging protocol and is a principal factor that decides the Web Services performance. When a mobile Web Service is implemented with the Java technology, it should be implemented with both a SOAP message processor like AXIS, and Java Servlet container (e.g. Tomcat). This typical implementation is not efficient because it requires an additional communication port and process. In this paper, we suggest a new method that replaces this typical approach to enhance Web Service performance.

• Journal of Korea Multimedia Society
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• v.13 no.10
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• pp.1514-1524
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• 2010

The standard Java class library does not support the platform-dependent features needed by the application. Therefore, the Java application including the platform -dependent features must supplement the required features by invoking native functions using JNI. The native language programmer has to explicitly specify how to connect to various Java objects and later to disconnect from them. In this paper, I suggest a way to avoid these annoying works. The native method in the pure java class can not contain a native code block. By providing a native code block for the native method, it is possible for programmer to write a native code without being aware of JNI. To achieve this, I introduced the native class that is a java class on the native environment, and made it possible to interchange data by placing an arbitrator between the java class and the native class.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.1101-1107
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• 2004

This paper presents an optimization algorithm and technique for designing parallel Cyclic Redundancy Check (CRC) circuit, which is most widely adopted for error detection A new heuristic algorithm is developed to find as many shared terms as possible, thus eventually to minimize the number and level of the exclusive-or logic blocks in parallel CRC circuits. 16-bit and 32-bit CRC generators are designed with different types of Programmable Logic Devices, and it has been found that our new algorithm and architecture significantly reduce the delay.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.6
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• pp.582-592
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• 2001

Video indexing plays an important role in the applications such as digital video libraries or web VOD which archive large volume of digital videos. Video indexing is usually based on video segmentation. In this paper, we propose a software tool called V2Web Studio which can generate video clips utilizing shot boundary detection algorithm. With the V2Web Studio, the process of clip generation consists of the following four steps: 1) Automatic detection of shot boundaries by parsing the video, 2) Elimination of errors by manually verifying the results of the detection, 3) Building a modeling structure of logical hierarchy using the verified shots, and 4) Generating multiple video clips corresponding to each logically modeled segment. The aforementioned steps are performed by shot detector, shot verifier, video modeler and clip generator in the V2Web Studio respectively.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2002.11a
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• pp.63-68
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• 2002

JPEG2000은 기존의 정지영상압축부호화 방식에 비해 우수한 비트율-왜곡(Rate-Distortion)특성과 향상된 주관적 화질을 제공하며 인터넷, 디지털 영상카메라, 이동단말기, 의학영상 등 다양한 분야에서 적용될 수 있는 새로운 정지영상압축 표준이다. 본 논문에서는 SoC(System on a Chip)설계를 고려한 JPEG2000 인코더의 구조를 제안하고 IP(Intellectual Property)를 설계 및 검증하였다. 구현된 JPEG2000 IP는 DWT(Discrete Wavelet Transform)블록, 스칼라양자화블록, EBCOT(Embedded Block Coding with Optimized Truncation)블록으로 구성되어 있다. IP는 모의실험을 통해 구현 구조에 대한 타당성을 검증하였고, 반도체설계자산연구센터에서 제시한 'RTL Coding Guideline'에 따라 HDL을 설계하였다. 특히, DWT블록은 구현시 많은 연산과 메모리 용량이 필요하므로 영상을 저장할 외부 메모리를 사용하였고, 빠른 곱셈과 덧셈연산을 위한 3단 파이프라인 부스곱셈기(3-state pipeline booth multiplier)와 캐리예측 덧셈기(carry lookahead adder)를 사용하였다. 설계된 JPEG2000 IP들은 삼성 0.35$\mu\textrm{m}$ 라이브러리를 이용하여 Synopsys사 Design Analyzer 틀을 통해 논리 합성하였으며, Xillinx 100만 게이트 FPGA칩에 구현하여 그 동작을 검증하였다. 또한, Hard IP 설계를 위해 Avanti사의 Apollo툴을 이용하여 Layout을 수행하였다.

• Proceedings of the CALSEC Conference
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• 2003.09a
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• pp.115-120
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• 2003

To execute business collaborations, the business process specification is required and it is generated from the business process model. ebXML, which is the XML-based B2B standard framework for organizations over the Internet, recommends process analyst and modeler to use UN/CEFACT Modeling Methodology for modeling. All the artifacts of the modeling and transformed results between different business models may be registered in the business library for the share and re-use. In this paper, we implement the business process modeler including built-in registry client. It provides not only modeling the business process but also generating the specifications, exporting the metadata about the business model, and registering in the business library.

• The Journal of Society for e-Business Studies
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• v.13 no.2
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• pp.1-21
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• 2008

Telematics services are being widely used recently. However, data sharing is restricted because data representations among telematics severs and terminals are not yet standardized. Moreover, changes of some data items can cause the modification of telematics software. To resolve the problem, we define an XML-based markup language, called tele-XML, for the standard representation of telematics data, and design a framework and related schema for the tele-XML. We also implement API libraries and program modules for the processing of tele-XML documents. By using the proposed representation and processing scheme, the previous problem can be resolved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.321-334
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• 2003

Globally-Asynchronous Locally-Synchronous (GALS) systems are worthy of notice as an adequate architecture for a large scaled chip design with guaranteeing easy designs and functional confidence. In this paper, we suggest an advanced structure of the interface unit which is indispensable for GALS systems by using stoppable clocks. The proposed interface unit is composed of a sender module and a receiver module. The sender module can carry out data transmission partially without the relation to an internal clock. We have designed it with 0.25${\mu}{\textrm}{m}$ standard cell library at the gate level and simulated its operation to show performance improvement. Finally, we constructed all example circuit with the interface unit and proved the correct operation of it.