• Title/Summary/Keyword: 라운드 보안 분야

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KpqC 공모전 1 라운드 격자 기반 PKE/KEM 알고리즘 분석

  • Joohee Lee
    • Review of KIISC
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    • v.33 no.3
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    • pp.39-47
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    • 2023
  • 양자컴퓨팅 기술이 발전함에 따라, 양자컴퓨터를 이용한 공격에도 안전한 암호인 양자내성암호(Post-Quantum Cryptography, PQC) 기술의 중요성이 대두되고 있다. NIST에서는 2016년부터 시작된 표준화 공모 1,2,3 라운드를 통해 2022년 공개키 암호 및 Key-establishment, 전자서명 분야의 양자내성암호 표준을 선정한 바 있으며, 현재는 4 라운드와 전자서명 분야 추가 선정 공모를 진행 중이다. 이러한 배경에서 2022년 국내에서도 양자내성암호 알고리즘 표준화 공모인 KpqC 공모전 1라운드를 시작하였고, 공개키 암호 및 Key-establishment 7종, 전자서명 9종의 알고리즘이 표준 후보로 제출되었다. 본고에서는 KpqC 공모전 1 라운드 공개키 암호 및 Key-establishment 알고리즘 중 격자 기반 공개키 암호/KEM(Key Encapsulation Mechanism) 알고리즘 3종 NTRU+, SMAUG, TiGER에 대해 분석 및 소개한다. 각 알고리즘의 기반 문제, 설계 방식, 특징, 안전성 분석 방식 등을 분석하고, 구현성능을 비교 분석한다.

A Study on the VCR Cryptographic System Design Adapted in Wire/Wireless Network Environments (유무선 네트워크 환경에 적합한 VCR 암호시스템 설계에 관한 연구)

  • Lee, Seon-Keun
    • Journal of the Korea Society of Computer and Information
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    • v.14 no.7
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    • pp.65-72
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    • 2009
  • This paper proposed VCR cryptographic algorithm that adapted in TCP/IP protocol architecture and wire/wireless communication network environments. we implemented by hardware chip level because proposed VCR cryptographic algorithm perform scalable & reconfigurable operations into the security system. Proposed VCR cryptographic algorithm strengthens security vulnerability of TCP/IP protocol and is very profitable real-time processing and encipherment of high-capacity data and multi-user communication because there is important purpose to keep security about many user as that have variable round numbers function in network environments.

Implementation of a High Performance SEED Processor for Smart Card Applications (스마트카드용 고성능 SEED 프로세서의 구현)

  • 최홍묵;최명렬
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.14 no.5
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    • pp.37-47
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    • 2004
  • The security of personal informations has been an important issue since the field of smart card applications has been expanded explosively. The security of smart card is based on cryptographic algorithms, which are highly required to be implemented into hardware for higher speed and stronger security. In this paper, a SEED cryptographic processor is designed by employing one round key generation block which generates 16 round keys without key registers and one round function block which is used iteratively. Both the round key generation block and the F function are using only one G function block with one 5${\times}$l MUX sequentially instead of 5 G function blocks. The proposed SEED processor has been implemented such that each round operation is divided into seven sub-rounds and each sub-round is executed per clock. Functional simulation of the proposed cryptographic processor has been executed using the test vectors which are offered by Korea Information Security Agency. In addition, we have evaluated the proposed SEED processor by executing VHDL synthesis and FPGA board test. The die area of the proposed SEED processor decreases up to approximately 40% compared with the conventional processor.

Design and Evaluation of A Block Encryption Algorithm using Dynamic-Key (동적 키를 이용한 블럭 암호 알고리즘의 설계 및 평가)

  • 정홍섭;이창두;박규석
    • Journal of Korea Multimedia Society
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    • v.5 no.6
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    • pp.683-696
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    • 2002
  • The existing block encryption algorithms have been designed for the encryption key value to be unchanged and applied to the round functions of each block, and enciphered. Therefore, it has such a weak point that the plaintext or encryption key could be easily exposed by differential cryptanalysis or linear cryptanalysis, both are the most powerful methods for decoding block encryption of a round-repeating structure. In order to overcome with this weak point, an encryption algorithm using a mote efficient key should be designed. In this paper, a block encryption algorithm which is designed for each encryption key value to be applied to each round block with different value is proposed. This algorithm needs a short processing time in an encryption and decryption, has a high intensity, can apply to electronic commerce and various applications of data protection.

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KpqC에 제출된 코드기반 암호의 소개 및 분석

  • Ji-Hoon Hong;Byung-Sun Won;Jon-Lark Kim
    • Review of KIISC
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    • v.33 no.3
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    • pp.49-57
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    • 2023
  • Shor 알고리즘의 영향으로 RSA 등 기존 잘 알려진 암호 알고리즘들은 양자컴퓨터가 등장하면 안전성에 대한 위험을 받게 된다. NIST에서는 양자컴퓨터 환경으로부터 보안성이 유지되는 암호를 선정하기 위한 양자내성암호 공모전을 개최하였다. 또한, 국내에서도 양자내성암호 분야의 경쟁력 향상과 기술 저변 확대를 위해 양자내성암호 국가공모전(KpqC 공모전)을 개최하였다. 본 논문은 KpqC 공모전 1라운드에 제출된 4개의 코드 기반 양자내성암호 알고리즘에 대한 소개, 퍼포먼스 및 안전성에 관하여 살펴볼 것이다.

Design of Encryption/Decryption Core for Block Cipher Camellia (Camellia 블록 암호의 암·복호화기 코어 설계)

  • Sonh, Seungil
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.4
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    • pp.786-792
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    • 2016
  • Camellia was jointly developed by Nippon Telegraph and Telephone Corporation and Mitsubishi Electric Corporation in 2000. Camellia specifies the 128-bit message block size and 128-, 192-, and 256-bit key sizes. In this paper, a modified round operation block which unifies a register setting for key schedule and a conventional round operation block is proposed. 16 ROMs needed for key generation and round operation are implemented using only 4 dual-port ROMs. Due to the use of a message buffer, encryption/decryption can be executed without a waiting time immediately after KA and KB are calculated. The suggested block cipher Camellia algorithm is designed using Verilog-HDL, implemented on Virtex4 device and operates at 184.898MHz. The designed cryptographic core has a maximum throughput of 1.183Gbps in 128-bit key mode and that of 876.5Mbps in 192 and 256-bit key modes. The cryptographic core of this paper is applicable to security module of the areas such as smart card, internet banking, e-commerce and satellite broadcasting.

양자내성암호 국가공모전

  • Nari Lee;Kyung Chul Jeong;Seongtaek Chee;Daewan Han
    • Review of KIISC
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    • v.33 no.3
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    • pp.7-14
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    • 2023
  • 1990년대에 P. Shor가 소개한 양자 알고리즘에 의해 양자컴퓨팅을 사용하여 다항식 시간 내에 인수분해나 이산대수 문제를 해결할 수 있다는 것이 알려졌다. 양자컴퓨터의 실용화가 기존 공개키 암호에 심각한 위협이 되는 것이다. 이에 대한 대응으로 많은 국가들이 양자내성암호 개발 및 표준화에 힘쓰고 있으며, 대표적으로 미국의 국립표준기술연구소(NIST)가2017년에 양자내성암호 표준화 공모사업을 시작하였다. 국내에서도 양자내성암호 분야의 활성화 및 자체 기술력 확보를 위해 노력하고 있다. 그 일환으로 국가보안기술연구소가 국가정보원의 후원으로 2021년에 발족한 양자내성암호연구단은 현재 '양자내성암호 국가공모전'을 진행하며 양자내성암호 개발에 힘쓰고 있다. 이 논문에서는 1라운드가진행중인양자내성암호 국가공모전의 추진 배경, 취지 및 진행 상황을 소개하고자 한다.

PQ-PoRR: Post-Quantum Blockchain Consensus Algorithm with Round-Robin (PQ-PoRR: 라운드로빈 기반 양자 내성 블록체인 합의 알고리즘)

  • Won-Woong Kim;Yea-Jun Kang;Hyun-Ji Kim;Yu-Jin Oh;Hwa-Jeong Seo
    • Proceedings of the Korea Information Processing Society Conference
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    • 2023.11a
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    • pp.257-259
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    • 2023
  • 양자 컴퓨터의 발전과 쇼어 알고리즘을 통한 ECC(Eliptic Curve Cryptography)에 대한 다항 시간의 솔루션을 제공함으로써 블록체인의 안정성이 위협받고 있다. 본 논문에서는 Round-Robin을 기반으로 하는 알고리즘을 제안함으로써 블록 생성에 대한 공정성을 제공하며 양자 내성 전자 서명인 CRYSTALS-DIlithium을 적용함으로써 근미래에 다가올 양자 위험성에 대비하였다. TPS 측면에서는 DIlithium의 큰 키 크기와 큰 서명 크기에 의해 ECDSA에 비해 낮은 성능을 보여주었지만, Latency 측면에서는 더욱 높은 성능을 보여주며, 이는 실시간성이 중요한 IoT와 같은 분야에서 더욱 높은 효용성을 보여줌을 알 수 있다.

A SPECK Crypto-Core Supporting Eight Block/Key Sizes (8가지 블록/키 크기를 지원하는 SPECK 암호 코어)

  • Yang, Hyeon-Jun;Shin, Kyung-Wook
    • Journal of IKEEE
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    • v.24 no.2
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    • pp.468-474
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    • 2020
  • This paper describes the hardware implementation of SPECK, a lightweight block cipher algorithm developed for the security of applications with limited resources such as IoT and wireless sensor networks. The block cipher SPECK crypto-core supports 8 block/key sizes, and the internal data-path was designed with 16-bit for small gate counts. The final round key to be used for decryption is pre-generated through the key initialization process and stored with the initial key, enabling the encryption/decryption for consecutive blocks. It was also designed to process round operations and key scheduling independently to increase throughput. The hardware operation of the SPECK crypto-core was validated through FPGA verification, and it was implemented with 1,503 slices on the Virtex-5 FPGA device, and the maximum operating frequency was estimated to be 98 MHz. When it was synthesized with a 180 nm process, the maximum operating frequency was estimated to be 163 MHz, and the estimated throughput was in the range of 154 ~ 238 Mbps depending on the block/key sizes.

A Study on AES Extension for Large-Scale Data (대형 자료를 위한 AES 확장에 관한 연구)

  • Oh, Ju-Young;Kouh, Hoon-Joon
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.9 no.6
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    • pp.63-68
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    • 2009
  • In the whole information technology area, the protection of information from hacking or tapping becomes a very serious issue. Therefore, the more effective, convenient and secure methods are required to make the safe operation. Encryption algorithms are known to be computationally intensive. They consume a significant amount of computing resources such as CPU time and memory. In this paper we propose the scalable encryption scheme with four criteria, the compression of plaintext, variable size of block, selectable round and software optimization. We have tested our scheme by c++. Experimental results show that our scheme achieves the faster execution speed of encryption/decryption.

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