• Journal of Digital Contents Society
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• v.17 no.2
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• pp.71-79
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• 2016

This study is intended to compare the performances of sound source localization methods used for stable automobile control by improving voice recognition rate in automobile environment and suggest how to improve their performances. Generally, sound source location estimation methods employ the TDOA algorithm, and there are two ways for it; one is to use a cross correlation function in the time domain, and the other is GCC-PHAT calculated in the frequency domain. Among these ways, GCC-PHAT is known to have stronger characteristics against echo and noise than the cross correlation function. This study compared the performances of the two methods above in automobile environment full of echo and vibration noise and suggested the use of a median filter additionally. We found that median filter helps both estimation methods have good performances and variance values to be decreased. According to the experimental results, there is almost no difference in the two methods' performances in the experiment using voice; however, using the signal of a song, GCC-PHAT is 10% more excellent than the cross correlation function in terms of the recognition rate. Also, when the median filter was added, the cross correlation function's recognition rate could be improved up to 11%. And in regarding to variance values, both methods showed stable performances.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.6-13
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• 2009

For X-band phased array systems, a power amplifier, a 6-bit phase shifter, a 6-bit digital attenuator, and a SPDT transmit/receive (T/R) switch are fabricated and measured. All circuits are demonstrated by using CMOS 0.18 um technology. The power amplifier has 2-stage differential and cascade structures. It provides 1-dB gain-compressed output power ($P_{1dB}$) of 20 dBm and power-added-efficiency (PAE) of 19 % at 8-11 GHz frequencies. The 6-bit phase shifter utilizes embedded switched filter structure which consists of nMOS transistors as a switch and meandered microstrip lines for desired inductances. It has $360^{\circ}$ phase-control range and $5.6^{\circ}$ phase resolution. At 8-11 GHz frequencies, it has RMS phase and amplitude errors are below $5^{\circ}$ and 0.8 dB, and insertion loss of $-15.7\;{\pm}\;1,1\;dB$. The 6-bit digital attenuator is comprised of embedded switched Pi-and T-type attenuators resistive networks and nMOS switches and employes compensation circuits for low insertion phase variation. It has max. attenuation of 31.5 dB and 0.5 dB amplitude resolution. Its RMS amplitude and phase errors are below 0.4 dB and $2^{\circ}$ at 8-11 GHz frequencies, and insertion loss is $-10.5\;{\pm}\;0.8\;dB$. The SPDT T/R switch has series and shunt transistor pairs on transmit and receive path, and only one inductance to reduce chip area. It shows insertion loss of -1.5 dB, return loss below -15 dB, and isolation about -30 dB. The fabricated chip areas are $1.28\;mm^2$, $1.9mm^2$, $0.34\;mm^2$, $0.02mm^2$, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1340-1350
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• 2009

The design and implementation of planar Active Phased Array Antenna System are described in this paper. This Antenna system operates at X-band with its bandwidth 10 % and dual polarization is realized using dual slot feeding microstrip patch antenna and SPDT(Single Pole Double Through) switch. Array Structure is $16\times16$ triangular lattice structure and each array is composed of TR(Transmit & Receive) module with more than 40 dBm power. Each TR module includes digital attenuator and phase shifter so that antenna beam can be electronically steered over a scan angle$({\pm}60^{\circ})$. Measurement of antenna pattern is conducted using a near field chamber and the results coincide with the expected beam pattern. From these results, it can be convinced that this antenna can be used with control of beam steering and beam shaping.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• 한국방재학회:학술대회논문집
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• 2011.02a
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• pp.101-101
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• 2011

현재 국내에서 시행되고 있는 '4대강 살리기 사업'은 하천에서 발생하는 홍수 및 가뭄재해방지를 위한 다양한 공학적 노력을 시도하고 있다. 특히 안정적인 수위 및 유량확보와 홍수방지를 위한 보(weir)가 4대강 유역에 16개 설치되고 있다. 이러한 보 구간에는 고정보와 가동보가 복합적으로 설치되고 있으며 가동보는 그 형상과 운영방식에 따라 다양한 설계방안이 적용되었다. '4대강 살리기 사업' 중 낙동강 23공구의 강정보 공사 구간에는 원호형태의 측면 형상을 갖는 라이징 섹터게이트(Rising sector gate)가 적용되었다. 라이징 섹터게이트는 구조물의 높이가 낮고 수문의 개폐장치가 수문피어 구조물 내에 설치되어 경관이 우수하며, 구조가 간단하여 비체와 수류의 안정성이 뛰어나기 때문에 4개의 공사구간에 적용되었다. 따라서 본 연구에서는 강정보의 가동보 구간 2문 중 1문을 1/100 축척으로 제작하여 가변경사 개수로에 설치하고, 홍수 빈도별 상류 유량 조건과 하류단 수위조건으로 케이스를 정하여 실험을 수행하였다. 본 실험에서 사용한 개수로 장치는 너비 0.6 m, 높이 0.8 m, 그리고 길이 15.0 m(측정가능 구간, 헤드탱크와 테일게이트 부제외)의 개수로 실험장치이다. 측부는 모두 강화유리로 되어 육안관찰 및 계측 시 용이하게 제작되었으며, 순환식 유량 공급장치를 구축하여 수로의 하부에 설치된 유량탱크로부터 계속적으로 순환하도록 설계되었다. 또한 수로 하단으로부터 상단방향으로 약 33 m 지점에 전동 유압식 Jack screw 2기가 설치되어 경사도를 조절할 수 있도록 제작되었다. 유량조절용 판넬의 제어기판에는 디지털 경사계가 설치되어 있기 때문에 보다 정확한 경사도의 조절이 가능하다. 보 모형의 총연장은 53 cm이며 폭은 45 cm이다. 섹터게이트의 게이트부분은 직경 15 cm로 설계하였다. 문주부분을 포함한 모든 모형은 아크릴로 제작하며 레이저의 주사를 방해하지 않으며 투과율을 최대로 할 수 있도록 고강도의 아크릴을 가장 얇게 하여 중공형태를 채택하였다. 실험조건은 우선 보의 운영방안에 따라 게이트의 4가지 개방도를 설정하였고, 특히 평수위조건에서는 보의 상류부에 퇴적된 퇴적물의 세척을 위한 flushing 운영개방도 포함되어 있다. 홍수시에 대한 유량조건은 2년 빈도에 해당하는 유량을 수문의 비율과 상사법칙에 따라 설정하였으며 하류단 수위조건도 동일한 조건에 대한 값을 채택하여 적용하였다. 유동장의 해석을 위해서는 비접촉식 계측방법인 PIV(Particle Image Velocimetry) 시스템을 채택하여 2차원(x-z 방향) laser sheet를 생성하고 주입된 particle에서 반사된 변위(displacement) 정보를 상호상관(cross-correlation)기법으로 유동장을 계산하였다. 또한 수리모형과 동일한 지형격자를 구축하여 3차원 CFD 프로그램인 FLOW-3D로 계산하여 결과를 비교하였다. 특히 flushing 운영방안에 대한 게이트부의 개방도를 세가지(30, 45, $60^{\circ}$)로 구분하여 모의하였고, 적절한 개방도를 제안하고자 하였다. 실험결과는 우선 4가지 운영방안에 대한 가동보 주변에서의 유속장을 파악하였고, 최대유속의 발생위치의 변화를 확인할 수 있었다. 그리고 이에 따른 보의 바닥에서 최대유속이 발생할 경우, 하상보호공 위치와 거리 등에 대해서 분석하였다. 이를 통해 가동보 운영에 따른 다양한 유속구조를 파악할 수 있게 되며 구조적 안정성 확보를 위한 검증자료로 활용될 수 있을 것으로 예상된다. 향후, 가동보 운영방안 중 수세효과(flushing effect)에 대한 효과분석을 위해 게이트부 상류구간에 적절한 입경과 비중의 퇴적물질을 설치하는 연구와 상류부에서의 유입유사농도 및 시간변화에 따른 퇴적에 관한 연구를 수행할 계획이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.6
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• pp.49-54
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• 2006

The X-ray unit developed by this study is to diagnose emergency cases which is too far from a hospital and to classify the patients. We have to use the X-ray in a ambulance or the scene of an accident where we cannot use the AC220 outlet because of the distance from a hospital as well. The X-ray unit developed has a characteristics as follows. First of all, as the unit has a condenser in itself where there is no electric supply, we can use the X-ray inspector in a mountain area or a island. Second, we can detect by digital detector the information taken by X-ray from DC 12[V] electricity and store as a form of file. A control circuit can secure the reliability of the X-ray unit by using the Pic16F84A X-ray and provide various functions. The X-ray unit which suits remote emergency system can be efficiently used for the emergent cases who is too far from a doctor and a hospital or in the situation where it is difficult to diagnose, transcribe and treat simultaneously.

• Cartoon and Animation Studies
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• s.40
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• pp.477-496
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• 2015

Emotional awareness is the image of a person is represented by different tendencies. Currently, the emotion computing to objectively evaluate the emotion recognition research is being actively studied. However, existing emotional computing research has many problems to run. First, the non-objective in emotion recognition if it is inaccurate. Second, the correlation between the emotion recognition is unclear points. So to test the regularity of image sensitivity to the need of the present study is to control emotions in the computing system. In addition, the screen number of the emotion recognized for the purpose of this study, applying the method of objective image emotional computing system and compared with a similar degree of emotion of the person. The key features of the image emotional computing system calculates the emotion recognized as numbered digital form. And to study the background of emotion computing is a key advantage of the effect of the James A. Russell for digitization of emotion (Core Affect). Pleasure emotions about the core axis (X axis) of pleasure and displeasure, tension (Y-axis) axis of tension and relaxation of emotion, emotion is applied to the computing research. Emotional axis with associated representative sensibility very happy, excited, elated, happy, contentment, calm, relaxing, quiet, tired, helpless, depressed, sad, angry, stress, anxiety, pieces 16 of tense emotional separated by a sensibility ComputingIt applies. Course of the present study is to use the color of the color key elements of the image computing formula sensitivity, brightness, and saturation applied to the sensitivity property elements. Property and calculating the rate sensitivity factors are applied to the importance weight, measured by free-level sensitivity score (X-axis) and the tension (Y-axis). Emotion won again expanded on the basis of emotion crossed point, and included a representative selection in Sensibility size of the top five ranking representative of the main emotion. In addition, measuring the emotional image of a person with 16 representative emotional score, and separated by a representative of the top five senses. Compare the main representative of the main representatives of Emotion and Sensibility people aware of the sensitivity of the results to verify the similarity degree computing emotion emotional emotions depending on the number of representative matches. The emotional similarity computing results represent the average concordance rate of major sensitivity was 51%, representing 2.5 sensibilities were consistent with the person's emotion recognition. Similar measures were the degree of emotion computing calculation and emotion recognition in this study who were given the objective criteria of the sensitivity calculation. Future research will need to be maintained weight room and the study of the emotional equation of a higher concordance rate improved.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.2
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• pp.138-148
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• 2001

Digital Video (DV) coding standards for digital video cassette recorder are based mainly on DCT and variable length coding. DV has low hardware complexity but high compressed bit rate of about 26 Mb/s. Thus, it is necessary to encode video with low complex video coding at the studios and then transcode compressed video into MPEG-2 for video-on-demand system. Because these coding methods exploit DCT, transcoding in the DCT domain can reduce computational complexity by excluding duplicated procedures. In transcoding DV into MPEC-2 intra coding, multiplying matrix by transformed data is used for 4:1:1-to-4:2:2 chroma format conversion and the conversion from 2-4-8 to 8-8 DCT mode, and therefore enables parallel processing. Variance of sub block for MPEG-2 rate control is computed completely in the DCT domain. These are verified through experiments. We estimate motion hierarchically using DCT coefficients for transcoding into MPEG-2 inter coding. First, we estimate motion of a macro block (MB) only with 4 DC values of 4 sub blocks and then estimate motion with 16-point MB using IDCT of 2$\times$2 low frequencies in each sub block, and finish estimation at a sub pixel as the fifth step. ME with overlapped search range shows better PSNR performance than ME without overlapping.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.573-582
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• 2010

In this paper, X-band transceiver for high resolution wideband SAR systems is designed and fabricated. Also as a technique for enhancing the performance, error compensation algorithm is presented. The transceiver for SAR system is composed of transmitter, receiver, switch matrix and frequency generator. The receiver especially has 2 channel mono-pulse structure for ground moving target indication. The transceiver is able to provide the deramping signal for high resolution mode and select the receive bandwidth for receiving according to the operation mode. The transceiver had over 300 MHz bandwidth in X-band and 13.3 dBm output power which is appropriate to drive the T/R module. The receiver gain and noise figure was 39 dB and 3.96 dB respectively. The receive dynamic range was 30 dB and amplitude imbalance and phase imbalance of I/Q channel was ${\pm}$0.38 dBm and ${\pm}$3.47 degree respectively. The transceiver meets the required electrical performances through the individual tests. This paper shows the pulse error term depending on SAR performance was analyzed and range IRF was enhanced by applying the compensation technique.