• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.17-22
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• 2008

This paper presents a low-power and small-area pulse width modulator by light intensity for photoflash. Light intensity controller is achieved by using capacitor, photodiode, and comparator. The proposed circuit designs digital circuit to reduce static power consumption except comparator. And IGBT driver has short circuit protection using delay cell. The pulse width modulator has the operating range of $V_{MS}$ from 0.5V to 2.5V and pulse width of output from 0.14ms to 1.65ms at 300Hz. The pulse width modulator fabricated in $0.35-{\mu}m$ CMOS technology occupies $0.85mm{\times}0.56mm$. This circuit consumes 3.0mW at 300Hz and 3.0V.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.34-41
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• 1998

An integrated circuit for magnetic stripe storage system is implemented. All the analog and digital circuits are integrated in one chip. The analog block contains preamplifier, peak detecter, comparator and reference generater. And digital block includes reference window signal generater, up/down counter for F/2F signal measurement, bit-error detection logic, and control logic. Both the encoding and decoding functions for F/2F signal processing are provided. An AGC(automatic gain control) circuit which was included in conventional circuits is eliminated due to optimized circuit design. Misreading prevention circuits are also proposed by fixing up new reference bit when broken bits are detected. The prototype chip is implemented using $0.8{\mu}m$ N-well CMOS technology and operates from 3.3 V to 7.5 V of supply voltage. It occupies a die area of $3.04mm^2(1.6mm{\times}1.9mm)$ and dissipates 8 mW with a 5 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.117-124
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• 2004

Various multimedia systems have been developed and their application areas widely proliferate. Thus, the interoperability is getting important among various networks and devices. The video transcoding is a technology to solve this interoperability problem among various coding standards. Transcoding can be defined as the conversion of one compressed coded data to another. In this paper, MPEG-2 to MPEG-4 transcoder in the spatial domain is compared with that in the DCT domain. The transcoder is very useful when a video sequence that is originally encoded for digital TV, DVD or satellite broadcasting is served in mobile environment. In order to compare two transcoders, all modules except motion compensation and down sampling are implemented identically. In addition, both transcoders do not search for motion vector. Instead, the decoded information is reused to the encoder. The experimental results show that the transcoder in the spatial domain is usually better than that in the DCT domain with respect to PSNR (Peak Signal-to-Noise Ratio), bitrate and execution time.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.20-26
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• 1999

A CMOS 6-bit 100MSPS ADC for DBS receiver is designed. The proposed ADC is composed of folding block, latch block, and digital block. The cascode interpolating block and kickback reduced latch are proposed with a high speed architecture. To verify the performance of ADC, simulations are carried out by HSPICE. The ADC achieves a clock frequency of 100MHz with a power dissipation of 40mW for 3 V supply voltage. The active chip area is $1500{\mu}m{\times}1000{\mu}m$with $0.65{\mu}m$ 2-poly 2-metal CMOS process. Further, INL and DNL are within ${\pm}0.6LSB$, ${\pm}0.5LSB$, respectively. SNDR is about 33dB at 10MHz input frequency.

• Journal of the Economic Geographical Society of Korea
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• v.23 no.3
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• pp.197-208
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• 2020

This study attempts to identify the structure of class conflict in Korea and to suggest an alternative framework for a empathetic society. The objective and subjective level of satisfaction with life and class consciousness are in direct proportion, and status consistency signifies polarization. Distorted distribution structures and cultural values make income disparity and property disputes widen, which in turn lead to educational divides and status fixations, refracting or blocking the possibility of social mobility. By overcoming the COVID-19 crisis, it is not appropriate to go back to the past but to correct wrong consciousness and practices in the past, and the consistency between the state and members of society must be re-established. Through the process of innovation at the economic, global, and digital level, a major transformation is required in the new normal era, which prioritizes social development for human values. The conflict resolution depends on the solidarity of the community as a social foundation, since an empathetic society needs the trust and communication of the members of the society.

• Composites Research
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• v.17 no.6
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• pp.28-36
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• 2004

Micro-tow deformation during forming of PVC foam-fabric composite sandwich structure is investigated to find out the correlation between forming condition and material deformation. The foams used in this research are PVC foams which have 4 different densities and the fabric composite is Carbon/epoxy prepreg which is plain weave (3k) as a skin material. Tow parameters such as crimp angle and tow amplitude are measured using microscope and a proper image tool and are compared with each other. In order to find out the effect of foam deformation during forming on tow deformation the compressive tests of foams are performed in three different environmental temperatures ($25^{\circ}C$, $80{\circ}C$, $125^{\circ}C$). The microscopic observation results show that the micro tow deformations are quite different from each other with respect to the foam density and forming pressure.

• Journal of IKEEE
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• v.17 no.3
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• pp.275-283
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• 2013

In this paper, a 8bit 10Ms/s CMOS Folding and Interpolation analog-to-digital convertor is proposed. The architecture of the proposed ADC is based on a Folding & Interpolation using FR(Folding Rate)=8, NFB(Number of Folding Block)=4, IR(Interpolation Rate)=8. The proposed ADC adopts a preamplifier sharing method to decrease the number of preamplifier by half comparing to the conventional ones. This chip has been fabricated with a 0.35[um] CMOS technology. The effective chip area is $1.8[mm]{\times}2.11[mm]$ and it consumes 20[mA] at 3.3 power supply with 10[MHz] clock. The INL is -0.57, +0.61 [LSB] and DNL is -0.4, +0.51 [LSB]. The SFDR is 48.9[dB] and SNDR is 47.9[dB](ENOB 7.6b) when the input frequency is 100[kHz] at 10[MHz] conversion rate.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.227-234
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• 2020

This paper introduces the state definition and diagnostic algorithm for autonomic control of manufacturing facilities. Smart factory systems through cyber-physical systems and digital twin technology are increasing the productivity and stability of existing manufacturing plants, which has become an issue recently. A Smart factory system is one of the key technologies that make up a smart factory system, to improve productivity, enable workers to make better decisions, and to control abnormal process flows. However, performing an autonomic control process based on large number of integrated plat data requires significant advance work. Therefore, in this paper, we define an abstracted facility state for manufacturing facility autonomic control and propose an algorithm to diagnose the current state. This makes the autonomic control process simpler by autonomic control based on the facility status rather then integrated facility data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.1-8
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• 2004

A novol clock distribution scheme is proposed for high-speed and low-power digital system to minimize clock skew and reduce dynamic power consumption. This scheme has ideal zero-skew characteristic by using folded clock lines (FCL) and phase blending circuit. For analyzing suitable line structures to FCLs, microstrip line and coplanar line are placed with folded clock lines. Simulation results show that the maximum clock-skew between two receivers located 10mm apart is less than lops at 1㎓ and the maximum clock-skew between two receivers located 20mm apart is less than 60ps at 1㎓. Also the results show that the minimum skews of clock signals regardless of process, voltage, and temperature variation are invariant.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.11
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• pp.61-66
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• 2005

This paper describes a 10-bit 210MHz CMOS current-mode Digital-to-Analog Converter (DAC) consisting of 6 bit MSB current cell matrix Sub-DAC, 2 bit mSB unary current source Sub-DAC, and 2 bit LSB binary weighting Sub-DAC for Wireless LAN application. A new deglitch circuit is proposed to control a crossing point of signals and minimize a glitch energy. The proposed 10-bit CMOS current mode DAC was designed by a $0.35{\mu}m$ CMOS double-poly four-metal technology rate of 210MHz, DNL/INL of ${\pm}0.7LSB/{\pm}1.1LSB$, a glitch energy of $76pV{\cdot}sec$, a SNR of 50dB, a SFDR of 53dB at 200MHz sampling clock and power dissipation of 83mW at 3.3V