• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.2
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• pp.15-21
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• 2008

This paper discuss the sequential digital logic systems and arithmetic operation algorithms which is the important material in computer architecture using analysis and synthesis which is based on extension logic for binary logic over galois fields. In sequential digital logic systems, we construct the moore model without feedback sequential logic systems after we obtain the next state function and output function using building block T-gate. Also, we obtain each algorithms of the addition, subtraction, multiplication, division based on the finite fields mathematical properties. Especially, in case of P=2 over GF($P^m$), the proposed algorithm have a advantage which will be able to apply traditional binary logic directly.The proposed method can construct more efficiency digital logic systems because it can be extended traditional binary logic to extension logic.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1773-1778
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• 2006

This paper propose the method of constructing the Digital Logic Systems based on the Improved Automatic Theorem Proving Techniques(IATP) over Finite Fields. The proposed method is as following. First, we discuss the background and the important mathematical properties for Finite Fields. Also, we discuss the concepts of the Automatic Theorem Proving Techniques(ATP) including the syntactic method and semantic method, and discuss the basic properties for the Alf. In this step, we define several definitions of the IAIP, Table Pseudo Function Tab and Equal. Next, we propose the T-gate as Building Block(BB) and describe the mathematical representation for the notation of T-gate. Then we discuss the important properties for the T-gate. Also, we propose the several relationships that are Identity relationship, Constant relationship, Tautology relationship and Mod R cyclic relationship. Then we propose Mod R negation gate and the manipulation of the don't care conditions. Finally, we propose the algorithm for the constructing the method of the digital logic systems over finite fields. The proposed method is more efficiency and regularity than my other earlier methods. Thet we prospect the future research and prospects.

• Proceedings of the Korea Multimedia Society Conference
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• 2002.11b
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• pp.587-592
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• 2002

본 논문에서는 De Bruijn 그래프에 기초한 다중처리기구성의 한 가지 방법을 제안하였다. 제안한 방법에서는 유한체상의 수학적 성질과 그래프의 성질을 사용하여 변환연산자를 제한하였으며, 이들 변환연산자를 이용하여 De Bruijn 그래프의 변환표를 도출하였다. 그리고, 이 변환표로부터 유한체상의 De Bruijn 그래프를 도출하였다. 제안한 다중처리기는 유한체상의 임의의 소수와 양의 정수에 대해 구성할 수 있으며 고장허용컴퓨팅시스템, 파이프라인 시스템, 병렬처리 네트워크, 스위칭 함수와 이의 회로, 차세대 디지털논리시스템 및 컴퓨터구조 중의 하나인 다치디지털논리시스템 등에 적용할 수 있으리라 전망된다.

• Journal of The Korean Association of Information Education
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• v.13 no.3
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• pp.341-349
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• 2009

In this paper, we proposed an Electric Circuit manipulation method to identify easily results of Digital Logic Circuits. Using this method for computer science educations, we can feasibly instruct and understand principles of a Digital Logic Circuit which is a basis of real Digital systems. Furthermore, we developed an PBL-based education program for Digital Logic Circuit concept and Boolean Algebra concept by applying the proposed Electric Circuit manipulation method and by explaining real life Digital Instrument examples. The experimental results are analyzed in views of the problem-solving ability and suitability of allocating degrees of difficulties to the developed Digital Logic Circuit problems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.675-676
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• 2013

This paper presents a design method for multiple-output combinational digital logic systems using time domain based on multiplexing and common multi-terminal extension decision diagrams. The common multi-terminal extension decision diagrams represents extension valued multiple-output functions, while time domain based on multiplexing systems transmit several signals on a single lines. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams, that is the common binary decision diagrams and common multi-terminal extension decision diagrams.

• 한국정보교육학회:학술대회논문집
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• 2006.08a
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• pp.109-115
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• 2006

오늘날 IT의 급속한 진보는 사회적, 경제적 변화를 가져왔다. 그리고 많은 나라들이 정보화시대에 선두를 차지하려 노력하고 있다. 이에 미래의 IT산업을 선도할 인재들의 첫 출발점이라고 할 수 있는 초등학교에서의 정보영재교육의 필요성이 더욱 중요시되고 있으며, 현대 디지털 사회 전 분야에 걸쳐 없어서는 안 될 필수적인 요소로 사용되고 있는 디지털 시스템의 동작 원리를 이해하는 것이 요구되고 있다. 이에 디지털 시스템의 동작 원리를 이해하는 데 기초가 되는 디지털 논리 회로에 대한 내용을 초등학교 아동들이 쉽고 흥미롭게 이해할 수 있는 교육방법을 개발하여 실생활에서 필요한 디지털 시스템을 창의적으로 설계하고, 이를 통한 문제해결능력을 향상하고자 한다.

• Journal of Engineering Education Research
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• v.6 no.1
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• pp.5-14
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• 2003

This paper presents a simplified web-based simulator for digital logic circuits with which several important principles related to digital logic circuits can be understood and confirmed. The proposed simulator is implemented to have several simplified functions which are essential to the learning process of digital logic circuits. The learners by themselves simulate several digital logic circuits on the web under specific input conditions and the design/analysis of digital logic circuits can be available. The proposed simulator, combined with multimedia contents, can be used as an auxiliary educational tool and enhance the improved learning efficiency. The results of this paper can be widely used to improve the efficiency of web-based educations in the cyber space. Several simulation results are illustrated as examples to show the validity of the proposed web-based simulator.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2000.11a
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• pp.15-18
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• 2000

인터넷을 포함한 여러 가지 기술이 발전됨에 따라 인터넷 광고 시장도 두드러지게 성장하고 있다. 무한한 가상 공간과 디지털이 갖는 신속성, 편리함 등 다양한 서비스를 제공할 수 있는 인터넷 기반의 모든 서비스는 데이터베이스로 축적된다. 여기에 애매함과 불확실성을 가지는 실세계를 표현하기 위해 퍼지논리함수를 이용하여 효율적으로 방문객을 분류하는 방법을 제시한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.721-724
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• 2006

This paper presents a method of the constructing the digital logic switching functions and realizing the circuit design using partition techniques. First of all, we introduce the necessity, background and concepts of the partition design techniques for the digital logic systems. Next, we discuss the definitions that are used in this paper. For the purpose of the circuit design for the digital logic switching functions, we discuss the extraction of the partition functions. Also we describe the construction method of the building block, that is called the building block, based on each partition functions. And we apply the proposed method to the example, and we compare the results with the results of the earlier methods. In result, we describe the control functions, it means that we obtain the effective cost in the digital logic design for any other earlier methods.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10a
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• pp.367-369
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• 2001

논리 회로는 하드웨어로 직접 구현할 수도 있으나, 설계된 디지털 논리를 프로그램으로 구현하고 이를 내장형 프로세서가 실행하게 하는 방식으로 구현할 수 있다. 이러한 구현은 내장형 시스템에 적합하도록 코드 크기와 실행 속도가 효율적이어야 한다. 본 논문에서는 복사 전파, 데드코드 삭제, 위상 정렬등의 컴파일러 최적화 기술과 함수 단위 모듈 개념을 도입하여 신호 흐름 분석 기법의 C 코드 자동 발생기를 구현하였다. 회로 시뮬레이션 구현 기법 중 유한 상태 천이 모델 기법으로 코드를 발생하는 Esterel 시스템과 성능 비교 실험을 한 결과, 코드 크기는 평균 84.17%로 감소되었으며 실행 속도는 평균 4.68배로 향상되었다.